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Searched refs:wptr_offs (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c76 unsigned wptr_offs, rptr_offs; in amdgpu_ih_ring_init() local
78 r = amdgpu_device_wb_get(adev, &wptr_offs); in amdgpu_ih_ring_init()
84 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
94 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
98 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
99 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; in amdgpu_ih_ring_init()
Dvcn_v2_5.c978 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_dec_ring_get_wptr()
995 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_dec_ring_set_wptr()
1062 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1067 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1086 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
1093 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
1157 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_jpeg_ring_get_wptr()
1174 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_jpeg_ring_set_wptr()
Damdgpu_ring.c273 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); in amdgpu_ring_init()
361 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); in amdgpu_ring_fini()
Dvcn_v2_0.c1455 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_dec_ring_get_wptr()
1476 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_dec_ring_set_wptr()
1679 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1684 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1703 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
1710 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
1819 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_jpeg_ring_get_wptr()
1836 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_jpeg_ring_set_wptr()
Dsdma_v4_0.c566 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_ring_get_wptr()
592 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_ring_set_wptr()
598 ring->wptr_offs, in sdma_v4_0_ring_set_wptr()
635 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_page_ring_get_wptr()
657 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_page_ring_set_wptr()
1038 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_gfx_resume()
1129 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_page_resume()
Dsdma_v5_0.c294 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); in sdma_v5_0_ring_get_wptr()
332 ring->wptr_offs, in sdma_v5_0_ring_set_wptr()
336 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
337 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
639 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v5_0_gfx_resume()
Dsdma_v3_0.c370 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; in sdma_v3_0_ring_get_wptr()
390 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
395 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
716 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v3_0_gfx_resume()
Dvce_v4_0.c85 return adev->wb.wb[ring->wptr_offs]; in vce_v4_0_ring_get_wptr()
108 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
179 adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0; in vce_v4_0_mmsch_start()
Damdgpu_ring.h206 unsigned wptr_offs; member
Duvd_v7_0.c121 return adev->wb.wb[ring->wptr_offs]; in uvd_v7_0_enc_ring_get_wptr()
156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
739 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; in uvd_v7_0_mmsch_start()
Dgfx_v10_0.c275 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx10_kiq_map_queues()
2809 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
2844 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
3028 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_gfx_mqd_init()
3307 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_compute_mqd_init()
4330 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_gfx()
4345 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v10_0_ring_set_wptr_gfx()
4364 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_compute()
4376 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v10_0_ring_set_wptr_compute()
Dgfx_v9_0.c3234 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_cp_gfx_resume()
3384 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_kiq_kcq_enable()
3511 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_mqd_init()
4964 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_gfx()
4979 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_gfx()
5153 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_compute()
5264 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_compute()
Dgfx_v8_0.c4326 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_cp_gfx_resume()
4413 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_kiq_kcq_enable()
4530 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_mqd_init()
6052 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_gfx()
6063 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_gfx()
6247 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_compute()
6255 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_compute()
Dgfx_v7_0.c2681 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v7_0_ring_get_wptr_compute()
2689 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v7_0_ring_set_wptr_compute()
2989 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_mqd_init()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dcik.c4178 wptr = rdev->wb.wb[ring->wptr_offs/4]; in cik_compute_get_wptr()
4194 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; in cik_compute_set_wptr()
8432 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET; in cik_startup()
8444 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET; in cik_startup()
Dradeon.h861 unsigned wptr_offs; member