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Searched refs:wptr (Results 1 – 25 of 88) sorted by relevance

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/Linux-v5.4/drivers/media/usb/pvrusb2/
Dpvrusb2-debugifc.c55 const char *wptr; in debugifc_isolate_word() local
60 wptr = NULL; in debugifc_isolate_word()
68 wptr = buf; in debugifc_isolate_word()
73 *wstrPtr = wptr; in debugifc_isolate_word()
182 const char *wptr; in pvr2_debugifc_do1cmd() local
186 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
189 if (!wptr) return 0; in pvr2_debugifc_do1cmd()
191 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); in pvr2_debugifc_do1cmd()
192 if (debugifc_match_keyword(wptr,wlen,"reset")) { in pvr2_debugifc_do1cmd()
193 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
[all …]
/Linux-v5.4/drivers/net/ppp/
Dbsd_comp.c580 unsigned char *wptr; in bsd_compress() local
586 if (wptr) \ in bsd_compress()
588 *wptr++ = (unsigned char) (v); \ in bsd_compress()
591 wptr = NULL; \ in bsd_compress()
630 wptr = obuf; in bsd_compress()
639 if (wptr) in bsd_compress()
641 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress()
642 *wptr++ = PPP_CONTROL(rptr); in bsd_compress()
643 *wptr++ = 0; in bsd_compress()
644 *wptr++ = PPP_COMP; in bsd_compress()
[all …]
Dppp_deflate.c190 unsigned char *wptr; in z_compress() local
204 wptr = obuf; in z_compress()
209 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
210 wptr[1] = PPP_CONTROL(rptr); in z_compress()
211 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress()
212 wptr += PPP_HDRLEN; in z_compress()
213 put_unaligned_be16(state->seqno, wptr); in z_compress()
214 wptr += DEFLATE_OVHD; in z_compress()
216 state->strm.next_out = wptr; in z_compress()
/Linux-v5.4/drivers/net/ethernet/tehuti/
Dtehuti.c168 f->wptr = 0; in bdx_fifo_init()
1104 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_rx_alloc_skbs()
1112 f->m.wptr += sizeof(struct rxf_desc); in bdx_rx_alloc_skbs()
1113 delta = f->m.wptr - f->m.memsz; in bdx_rx_alloc_skbs()
1115 f->m.wptr = delta; in bdx_rx_alloc_skbs()
1124 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); in bdx_rx_alloc_skbs()
1159 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_recycle_skb()
1167 f->m.wptr += sizeof(struct rxf_desc); in bdx_recycle_skb()
1168 delta = f->m.wptr - f->m.memsz; in bdx_recycle_skb()
1170 f->m.wptr = delta; in bdx_recycle_skb()
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/amdkfd/
Dkfd_kernel_queue.c215 uint32_t wptr, rptr; in acquire_packet_buffer() local
225 wptr = kq->pending_wptr; in acquire_packet_buffer()
231 pr_debug("wptr: %d\n", wptr); in acquire_packet_buffer()
234 available_size = (rptr + queue_size_dwords - 1 - wptr) % in acquire_packet_buffer()
245 if (wptr + packet_size_in_dwords >= queue_size_dwords) { in acquire_packet_buffer()
253 while (wptr > 0) { in acquire_packet_buffer()
254 queue_address[wptr] = kq->nop_packet; in acquire_packet_buffer()
255 wptr = (wptr + 1) % queue_size_dwords; in acquire_packet_buffer()
260 *buffer_ptr = &queue_address[wptr]; in acquire_packet_buffer()
261 kq->pending_wptr = wptr + packet_size_in_dwords; in acquire_packet_buffer()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c147 u32 wptr; in amdgpu_ih_process() local
152 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
159 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); in amdgpu_ih_process()
164 while (ih->rptr != wptr && --count) { in amdgpu_ih_process()
173 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
174 if (wptr != ih->rptr) in amdgpu_ih_process()
Dcz_ih.c192 u32 wptr, tmp; in cz_ih_get_wptr() local
194 wptr = le32_to_cpu(*ih->wptr_cpu); in cz_ih_get_wptr()
196 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in cz_ih_get_wptr()
197 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in cz_ih_get_wptr()
203 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
204 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
209 return (wptr & ih->ptr_mask); in cz_ih_get_wptr()
Diceland_ih.c192 u32 wptr, tmp; in iceland_ih_get_wptr() local
194 wptr = le32_to_cpu(*ih->wptr_cpu); in iceland_ih_get_wptr()
196 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in iceland_ih_get_wptr()
197 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in iceland_ih_get_wptr()
203 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
204 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
209 return (wptr & ih->ptr_mask); in iceland_ih_get_wptr()
Dsi_ih.c107 u32 wptr, tmp; in si_ih_get_wptr() local
109 wptr = le32_to_cpu(*ih->wptr_cpu); in si_ih_get_wptr()
111 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in si_ih_get_wptr()
112 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in si_ih_get_wptr()
114 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
115 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
120 return (wptr & ih->ptr_mask); in si_ih_get_wptr()
Dcik_ih.c190 u32 wptr, tmp; in cik_ih_get_wptr() local
192 wptr = le32_to_cpu(*ih->wptr_cpu); in cik_ih_get_wptr()
194 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in cik_ih_get_wptr()
195 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in cik_ih_get_wptr()
201 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
202 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
207 return (wptr & ih->ptr_mask); in cik_ih_get_wptr()
Dnavi10_ih.c213 u32 wptr, reg, tmp; in navi10_ih_get_wptr() local
215 wptr = le32_to_cpu(*ih->wptr_cpu); in navi10_ih_get_wptr()
217 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in navi10_ih_get_wptr()
221 wptr = RREG32_NO_KIQ(reg); in navi10_ih_get_wptr()
222 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in navi10_ih_get_wptr()
224 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in navi10_ih_get_wptr()
230 tmp = (wptr + 32) & ih->ptr_mask; in navi10_ih_get_wptr()
233 wptr, ih->rptr, tmp); in navi10_ih_get_wptr()
241 return (wptr & ih->ptr_mask); in navi10_ih_get_wptr()
Dtonga_ih.c194 u32 wptr, tmp; in tonga_ih_get_wptr() local
196 wptr = le32_to_cpu(*ih->wptr_cpu); in tonga_ih_get_wptr()
198 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in tonga_ih_get_wptr()
199 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in tonga_ih_get_wptr()
205 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
206 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
211 return (wptr & ih->ptr_mask); in tonga_ih_get_wptr()
Dvega10_ih.c376 u32 wptr, reg, tmp; in vega10_ih_get_wptr() local
378 wptr = le32_to_cpu(*ih->wptr_cpu); in vega10_ih_get_wptr()
380 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
394 wptr = RREG32_NO_KIQ(reg); in vega10_ih_get_wptr()
395 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
398 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in vega10_ih_get_wptr()
404 tmp = (wptr + 32) & ih->ptr_mask; in vega10_ih_get_wptr()
407 wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
424 return (wptr & ih->ptr_mask); in vega10_ih_get_wptr()
541 uint32_t wptr = cpu_to_le32(entry->src_data[0]); in vega10_ih_self_irq() local
[all …]
Dsdma_v5_0.c240 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ in sdma_v5_0_ring_init_cond_exec()
254 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v5_0_ring_patch_cond_exec()
289 u64 *wptr = NULL; in sdma_v5_0_ring_get_wptr() local
294 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); in sdma_v5_0_ring_get_wptr()
295 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); in sdma_v5_0_ring_get_wptr()
296 *wptr = (*wptr) >> 2; in sdma_v5_0_ring_get_wptr()
297 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); in sdma_v5_0_ring_get_wptr()
301 wptr = &local_wptr; in sdma_v5_0_ring_get_wptr()
307 *wptr = highbit; in sdma_v5_0_ring_get_wptr()
308 *wptr = (*wptr) << 32; in sdma_v5_0_ring_get_wptr()
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Dsdma_v4_0.c562 u64 wptr; in sdma_v4_0_ring_get_wptr() local
566 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_ring_get_wptr()
567 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v4_0_ring_get_wptr()
569 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); in sdma_v4_0_ring_get_wptr()
570 wptr = wptr << 32; in sdma_v4_0_ring_get_wptr()
571 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); in sdma_v4_0_ring_get_wptr()
573 ring->me, wptr); in sdma_v4_0_ring_get_wptr()
576 return wptr >> 2; in sdma_v4_0_ring_get_wptr()
599 lower_32_bits(ring->wptr << 2), in sdma_v4_0_ring_set_wptr()
600 upper_32_bits(ring->wptr << 2)); in sdma_v4_0_ring_set_wptr()
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Dvcn_v2_5.c671 ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_start()
866 ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start()
868 lower_32_bits(ring->wptr)); in vcn_v2_5_start()
870 WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
871 WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
877 WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
878 WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
995 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_dec_ring_set_wptr()
996 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vcn_v2_5_dec_ring_set_wptr()
998 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_dec_ring_set_wptr()
[all …]
Dvcn_v2_0.c723 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_start()
1047 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start_dpg_mode()
1049 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
1203 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start()
1205 lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1208 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1209 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1215 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1216 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1365 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
[all …]
/Linux-v5.4/drivers/gpu/drm/radeon/
Dradeon_ring.c88 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
129 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
177 while (ring->wptr & ring->align_mask) { in radeon_ring_commit()
215 ring->wptr = ring->wptr_old; in radeon_ring_undo()
312 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
472 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info() local
478 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info()
480 wptr, wptr); in radeon_debugfs_ring_info()
494 ring->wptr, ring->wptr); in radeon_debugfs_ring_info()
Dvce_v1_0.c97 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
99 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
299 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
305 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
306 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
/Linux-v5.4/drivers/video/fbdev/
Dmaxinefb.c67 unsigned char *wptr; in maxinefb_ims332_write_register() local
69 wptr = regs + 0xa0000 + (regno << 4); in maxinefb_ims332_write_register()
71 *((volatile unsigned short *) (wptr)) = val; in maxinefb_ims332_write_register()
/Linux-v5.4/drivers/infiniband/hw/cxgb3/
Dcxio_hal.c584 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len, in cxio_hal_ctrl_qp_write_mem()
588 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
592 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i); in cxio_hal_ctrl_qp_write_mem()
595 rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
604 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % in cxio_hal_ctrl_qp_write_mem()
646 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % in cxio_hal_ctrl_qp_write_mem()
650 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr; in cxio_hal_ctrl_qp_write_mem()
657 Q_GENBIT(rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
663 rdev_p->ctrl_qp.wptr++; in cxio_hal_ctrl_qp_write_mem()
681 u32 wptr; in __cxio_tpt_op() local
[all …]
Dcxio_wr.h46 #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) argument
47 #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ argument
48 ((rptr)!=(wptr)) )
50 #define Q_FREECNT(rptr,wptr,size_log2) ((1UL<<size_log2)-((wptr)-(rptr))) argument
51 #define Q_COUNT(rptr,wptr) ((wptr)-(rptr)) argument
697 u32 wptr; /* idx to next available WR slot */ member
718 u32 wptr; member
/Linux-v5.4/drivers/gpu/drm/msm/adreno/
Da5xx_preempt.c43 uint32_t wptr; in update_wptr() local
49 wptr = get_wptr(ring); in update_wptr()
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
136 a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring); in a5xx_preempt_trigger()
210 a5xx_gpu->preempt[i]->wptr = 0; in a5xx_preempt_hw_init()
Dadreno_gpu.c489 uint32_t wptr; in adreno_flush() local
499 wptr = get_wptr(ring); in adreno_flush()
504 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); in adreno_flush()
510 uint32_t wptr = get_wptr(ring); in adreno_idle() local
513 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) in adreno_idle()
518 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); in adreno_idle()
539 state->ring[i].wptr = get_wptr(gpu->rb[i]); in adreno_gpu_state_get()
542 size = state->ring[i].wptr; in adreno_gpu_state_get()
545 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) in adreno_gpu_state_get()
719 drm_printf(p, " wptr: %d\n", state->ring[i].wptr); in adreno_show()
[all …]
/Linux-v5.4/drivers/tty/serial/
Dmen_z135_uart.c298 u32 wptr; in men_z135_handle_tx() local
320 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_handle_tx()
321 txc = (wptr >> 16) & 0x3ff; in men_z135_handle_tx()
322 wptr &= 0x3ff; in men_z135_handle_tx()
338 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) in men_z135_handle_tx()
339 n = 4 - BYTES_TO_ALIGN(wptr); in men_z135_handle_tx()
459 u32 wptr; in men_z135_tx_empty() local
462 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_tx_empty()
463 txc = (wptr >> 16) & 0x3ff; in men_z135_tx_empty()

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