| /Linux-v5.4/drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi_wp.c | 20 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
44 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
46 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
49 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
51 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
53 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
56 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
58 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
61 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
[all …]
|
| D | hdmi.h | 238 struct hdmi_wp_data *wp; member
260 struct hdmi_wp_data *wp; member
295 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
296 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
297 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
298 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
299 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
300 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
301 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
302 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
[all …]
|
| D | hdmi5.c | 65 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler() local
68 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
69 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
93 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
96 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
101 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
103 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
169 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff); in hdmi_power_on_full()
170 hdmi_wp_set_irqstatus(&hdmi->wp, in hdmi_power_on_full()
[all …]
|
| D | hdmi4.c | 64 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler() local
67 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
68 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
78 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
80 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
83 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
85 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
87 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
147 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_power_on_full() local
156 hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE); in hdmi_power_on_full()
[all …]
|
| D | hdmi_pll.c | 42 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
50 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
60 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
63 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
147 if (hpll->wp->version == 4) in hdmi_init_pll_data()
162 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) in hdmi_pll_init() argument
168 pll->wp = wp; in hdmi_pll_init()
|
| D | hdmi4_cec.c | 176 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
177 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
178 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
190 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); in hdmi_cec_adap_enable()
213 hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
250 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
338 struct hdmi_wp_data *wp) in hdmi4_cec_init() argument
349 core->wp = wp; in hdmi4_cec_init()
352 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi4_cec_init()
|
| /Linux-v5.4/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi_wp.c | 21 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
45 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
47 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
50 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
52 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
54 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
57 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
59 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
62 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
[all …]
|
| D | hdmi.h | 233 struct hdmi_wp_data *wp; member
277 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
278 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
279 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
280 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
281 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
282 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
283 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
284 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
285 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
[all …]
|
| D | hdmi5.c | 65 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
68 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
69 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
93 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
96 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
101 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
103 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
178 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); in hdmi_power_on_full()
179 hdmi_wp_set_irqstatus(&hdmi.wp, in hdmi_power_on_full()
[all …]
|
| D | hdmi4.c | 61 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
64 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
65 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
75 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
77 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
80 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
82 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
84 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
148 struct hdmi_wp_data *wp = &hdmi.wp; in hdmi_power_on_full() local
156 hdmi_wp_clear_irqenable(wp, 0xffffffff); in hdmi_power_on_full()
[all …]
|
| D | hdmi_pll.c | 102 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
107 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
117 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
119 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
220 struct hdmi_wp_data *wp) in hdmi_pll_init() argument
225 pll->wp = wp; in hdmi_pll_init()
|
| /Linux-v5.4/arch/powerpc/math-emu/ |
| D | math_efp.c | 108 u32 wp[2]; member
199 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
200 vc.wp[1] = regs->gpr[fc]; in do_spe_mathemu()
201 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
202 va.wp[1] = regs->gpr[fa]; in do_spe_mathemu()
203 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
204 vb.wp[1] = regs->gpr[fb]; in do_spe_mathemu()
209 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
210 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
211 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
[all …]
|
| /Linux-v5.4/tools/testing/selftests/breakpoints/ |
| D | breakpoint_test_arm64.c | 81 static bool set_watchpoint(pid_t pid, int size, int wp) in set_watchpoint() argument
83 const volatile uint8_t *addr = &var[32 + wp]; in set_watchpoint()
112 static bool arun_test(int wr_size, int wp_size, int wr, int wp) in arun_test() argument
143 if (!set_watchpoint(pid, wp_size, wp)) in arun_test()
204 int wr, wp, size; in main() local
216 for (wp = wr - size; wp <= wr + size; wp = wp + size) { in main()
217 result = run_test(size, MIN(size, 8), wr, wp); in main()
218 if ((result && wr == wp) || in main()
219 (!result && wr != wp)) in main()
222 size, wr, wp); in main()
[all …]
|
| /Linux-v5.4/sound/hda/ |
| D | hdac_controller.c | 69 bus->rirb.wp = bus->rirb.rp = 0; in snd_hdac_bus_init_cmd_io()
144 unsigned int wp, rp; in snd_hdac_bus_send_cmd() local
151 wp = snd_hdac_chip_readw(bus, CORBWP); in snd_hdac_bus_send_cmd()
152 if (wp == 0xffff) { in snd_hdac_bus_send_cmd()
157 wp++; in snd_hdac_bus_send_cmd()
158 wp %= AZX_MAX_CORB_ENTRIES; in snd_hdac_bus_send_cmd()
161 if (wp == rp) { in snd_hdac_bus_send_cmd()
168 bus->corb.buf[wp] = cpu_to_le32(val); in snd_hdac_bus_send_cmd()
169 snd_hdac_chip_writew(bus, CORBWP, wp); in snd_hdac_bus_send_cmd()
187 unsigned int rp, wp; in snd_hdac_bus_update_rirb() local
[all …]
|
| D | hdac_bus.c | 134 unsigned int wp; in snd_hdac_bus_queue_event() local
140 wp = (bus->unsol_wp + 1) % HDA_UNSOL_QUEUE_SIZE; in snd_hdac_bus_queue_event()
141 bus->unsol_wp = wp; in snd_hdac_bus_queue_event()
143 wp <<= 1; in snd_hdac_bus_queue_event()
144 bus->unsol_queue[wp] = res; in snd_hdac_bus_queue_event()
145 bus->unsol_queue[wp + 1] = res_ex; in snd_hdac_bus_queue_event()
|
| /Linux-v5.4/arch/ia64/kernel/ |
| D | patch.c | 147 u64 *wp; in ia64_patch_mckinley_e9() local
160 wp = (u64 *) ia64_imva((char *) offp + *offp); in ia64_patch_mckinley_e9()
161 wp[0] = 0x0000000100000011UL; /* nop.m 0; nop.i 0; br.ret.sptk.many b6 */ in ia64_patch_mckinley_e9()
162 wp[1] = 0x0084006880000200UL; in ia64_patch_mckinley_e9()
163 wp[2] = 0x0000000100000000UL; /* nop.m 0; nop.i 0; nop.i 0 */ in ia64_patch_mckinley_e9()
164 wp[3] = 0x0004000000000200UL; in ia64_patch_mckinley_e9()
165 ia64_fc(wp); ia64_fc(wp + 2); in ia64_patch_mckinley_e9()
|
| /Linux-v5.4/lib/mpi/ |
| D | generic_mpih-lshift.c | 28 mpihelp_lshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned int cnt) in mpihelp_lshift() argument
36 wp += 1; in mpihelp_lshift()
44 wp[i] = (high_limb << sh_1) | (low_limb >> sh_2); in mpihelp_lshift()
47 wp[i] = high_limb << sh_1; in mpihelp_lshift()
|
| D | generic_mpih-rshift.c | 29 mpihelp_rshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned cnt) in mpihelp_rshift() argument
37 wp -= 1; in mpihelp_rshift()
44 wp[i] = (low_limb >> sh_1) | (high_limb << sh_2); in mpihelp_rshift()
47 wp[i] = low_limb >> sh_1; in mpihelp_rshift()
|
| /Linux-v5.4/lib/raid6/ |
| D | neon.uc | 62 register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
70 wq$$ = wp$$ = vld1q_u8(&dptr[z0][d+$$*NSIZE]);
73 wp$$ = veorq_u8(wp$$, wd$$);
81 vst1q_u8(&p[d+NSIZE*$$], wp$$);
93 register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
102 wp$$ = veorq_u8(vld1q_u8(&p[d+$$*NSIZE]), wq$$);
107 wp$$ = veorq_u8(wp$$, wd$$);
149 vst1q_u8(&p[d+NSIZE*$$], wp$$);
|
| D | int.uc | 88 unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
95 wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
98 wp$$ ^= wd$$;
105 *(unative_t *)&p[d+NSIZE*$$] = wp$$;
117 unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
125 wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
128 wp$$ ^= wd$$;
142 *(unative_t *)&p[d+NSIZE*$$] ^= wp$$;
|
| /Linux-v5.4/drivers/block/ |
| D | null_blk_zoned.c | 43 zone->wp = zone->start + zone->len; in null_zone_init()
53 zone->start = zone->wp = sector; in null_zone_init()
102 if (sector != zone->wp) in null_zone_write()
108 zone->wp += nr_sectors; in null_zone_write()
109 if (zone->wp == zone->start + zone->len) in null_zone_write()
134 zone[i].wp = zone[i].start; in null_zone_reset()
142 zone->wp = zone->start; in null_zone_reset()
|
| /Linux-v5.4/drivers/net/wireless/realtek/rtw88/ |
| D | pci.h | 130 static inline int avail_desc(u32 wp, u32 rp, u32 len) in avail_desc() argument
132 if (rp > wp) in avail_desc()
133 return rp - wp - 1; in avail_desc()
135 return len - wp + rp - 1; in avail_desc()
159 u32 wp; member
233 buf_desc = ring->r.head + ring->r.wp * size; in get_tx_buffer_desc()
|
| /Linux-v5.4/sound/pci/lola/ |
| D | lola.c | 89 unsigned int wp = chip->corb.wp + 1; in corb_send_verb() local
90 wp %= LOLA_CORB_ENTRIES; in corb_send_verb()
91 chip->corb.wp = wp; in corb_send_verb()
92 chip->corb.buf[wp * 2] = cpu_to_le32(data); in corb_send_verb()
93 chip->corb.buf[wp * 2 + 1] = cpu_to_le32(extdata); in corb_send_verb()
94 lola_writew(chip, BAR0, CORBWP, wp); in corb_send_verb()
112 unsigned int rp, wp; in lola_update_rirb() local
115 wp = lola_readw(chip, BAR0, RIRBWP); in lola_update_rirb()
116 if (wp == chip->rirb.wp) in lola_update_rirb()
118 chip->rirb.wp = wp; in lola_update_rirb()
[all …]
|
| /Linux-v5.4/arch/arm/boot/dts/ |
| D | rk3288-veyron-mighty.dts | 23 wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
25 /delete-property/ disable-wp;
30 sdmmc_wp_gpio: sdmmc-wp-gpio {
|
| /Linux-v5.4/arch/arm/kernel/ |
| D | hw_breakpoint.c | 688 struct perf_event *wp, **slots; in watchpoint_handler() local
697 wp = slots[i]; in watchpoint_handler()
699 if (wp == NULL) in watchpoint_handler()
702 info = counter_arch_bp(wp); in watchpoint_handler()
711 info->trigger = wp->attr.bp_addr; in watchpoint_handler()
733 if (!(access & hw_breakpoint_type(wp))) in watchpoint_handler()
742 perf_bp_event(wp, regs); in watchpoint_handler()
749 if (is_default_overflow_handler(wp)) in watchpoint_handler()
750 enable_single_step(wp, instruction_pointer(regs)); in watchpoint_handler()
760 struct perf_event *wp, **slots; in watchpoint_single_step_handler() local
[all …]
|
