Searched refs:wb_gpu_addr (Results 1 – 5 of 5) sorted by relevance
2981 uint64_t hqd_gpu_addr, wb_gpu_addr; in gfx_v10_0_gfx_mqd_init() local3022 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v10_0_gfx_mqd_init()3023 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_gfx_mqd_init()3025 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v10_0_gfx_mqd_init()3028 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_gfx_mqd_init()3029 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_gfx_mqd_init()3030 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v10_0_gfx_mqd_init()3223 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v10_0_compute_mqd_init() local3301 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v10_0_compute_mqd_init()3302 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_compute_mqd_init()[all …]
2934 u64 wb_gpu_addr; in gfx_v7_0_mqd_init() local2989 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_mqd_init()2990 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v7_0_mqd_init()2991 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v7_0_mqd_init()2994 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v7_0_mqd_init()2995 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v7_0_mqd_init()2997 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v7_0_mqd_init()
3416 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v9_0_mqd_init() local3505 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v9_0_mqd_init()3506 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v9_0_mqd_init()3508 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v9_0_mqd_init()3511 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_mqd_init()3512 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v9_0_mqd_init()3513 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v9_0_mqd_init()
4461 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; in gfx_v8_0_mqd_init() local4524 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v8_0_mqd_init()4525 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()4527 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v8_0_mqd_init()4530 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_mqd_init()4531 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()4532 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v8_0_mqd_init()
4530 u64 wb_gpu_addr; in cik_cp_compute_resume() local4691 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET; in cik_cp_compute_resume()4693 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET; in cik_cp_compute_resume()4694 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; in cik_cp_compute_resume()4695 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in cik_cp_compute_resume()4702 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET; in cik_cp_compute_resume()4704 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET; in cik_cp_compute_resume()4705 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc; in cik_cp_compute_resume()4707 upper_32_bits(wb_gpu_addr) & 0xffff; in cik_cp_compute_resume()
