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Searched refs:vm_manager (Results 1 – 25 of 38) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vm.c104 adev->vm_manager.block_size; in amdgpu_vm_level_shift()
129 adev->vm_manager.root_level); in amdgpu_vm_num_entries()
131 if (level == adev->vm_manager.root_level) in amdgpu_vm_num_entries()
133 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift; in amdgpu_vm_num_entries()
154 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_num_ats_entries()
170 if (level <= adev->vm_manager.root_level) in amdgpu_vm_entries_mask()
371 cursor->level = adev->vm_manager.root_level; in amdgpu_vm_pt_start()
707 unsigned level = adev->vm_manager.root_level; in amdgpu_vm_clear_bo()
989 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
1027 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_flush()
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Damdgpu_ids.c203 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
226 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
227 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
339 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
412 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab()
475 id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_alloc_reserved()
502 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_free_reserved()
525 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_reset()
552 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_reset_all()
572 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_mgr_init()
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Dgfxhub_v2_0.c93 + adev->vm_manager.vram_base_offset; in gfxhub_v2_0_init_system_aperture_regs()
207 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
224 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
233 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
235 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
Dgfxhub_v1_0.c98 + adev->vm_manager.vram_base_offset; in gfxhub_v1_0_init_system_aperture_regs()
207 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
208 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
245 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
247 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
Damdgpu_vm.h50 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
336 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib…
337 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->wri…
338 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_fu…
Dmmhub_v2_0.c78 adev->vm_manager.vram_base_offset; in mmhub_v2_0_init_system_aperture_regs()
196 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
214 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
223 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
225 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
Dgmc_v6_0.c463 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()
522 field = adev->vm_manager.fragment_size; in gmc_v6_0_gart_enable()
546 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
567 ((adev->vm_manager.block_size - 9) in gmc_v6_0_gart_enable()
899 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v6_0_sw_init()
907 adev->vm_manager.vram_base_offset = tmp; in gmc_v6_0_sw_init()
909 adev->vm_manager.vram_base_offset = 0; in gmc_v6_0_sw_init()
Dmmhub_v1_0.c122 adev->vm_manager.vram_base_offset; in mmhub_v1_0_init_system_aperture_regs()
239 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
240 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
277 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
279 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
Dmmhub_v9_4.c132 adev->vm_manager.vram_base_offset; in mmhub_v9_4_init_system_aperture_regs()
293 adev->vm_manager.num_level); in mmhub_v9_4_setup_vmid_config()
311 adev->vm_manager.block_size - 9); in mmhub_v9_4_setup_vmid_config()
327 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v9_4_setup_vmid_config()
331 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v9_4_setup_vmid_config()
Dgmc_v9_0.c631 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v9_0_get_vm_pde()
955 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); in gmc_v9_0_vram_gtt_location()
958 adev->vm_manager.vram_base_offset += in gmc_v9_0_vram_gtt_location()
1133 adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1229 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v9_0_sw_init()
1230 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v9_0_sw_init()
1231 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v9_0_sw_init()
Dgmc_v7_0.c548 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
620 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
649 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
667 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1028 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v7_0_sw_init()
1036 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1038 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
Damdgpu_csa.c29 uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; in amdgpu_csa_vaddr()
Dgmc_v10_0.c442 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v10_0_get_vm_pde()
528 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev); in gmc_v10_0_vram_gtt_location()
715 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v10_0_sw_init()
716 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v10_0_sw_init()
Dgmc_v8_0.c775 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
848 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
892 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
917 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
1154 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v8_0_sw_init()
1162 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1164 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
Dsi_dma.c840 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; in si_dma_set_vm_pte_funcs()
843 adev->vm_manager.vm_pte_rqs[i] = in si_dma_set_vm_pte_funcs()
846 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()
Damdgpu_vm_sdma.c238 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * in amdgpu_vm_sdma_update()
Dsdma_v2_4.c1266 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; in sdma_v2_4_set_vm_pte_funcs()
1269 adev->vm_manager.vm_pte_rqs[i] = in sdma_v2_4_set_vm_pte_funcs()
1272 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; in sdma_v2_4_set_vm_pte_funcs()
Dcik_sdma.c1378 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; in cik_sdma_set_vm_pte_funcs()
1381 adev->vm_manager.vm_pte_rqs[i] = in cik_sdma_set_vm_pte_funcs()
1384 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; in cik_sdma_set_vm_pte_funcs()
Dsdma_v5_0.c1727 if (adev->vm_manager.vm_pte_funcs == NULL) { in sdma_v5_0_set_vm_pte_funcs()
1728 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; in sdma_v5_0_set_vm_pte_funcs()
1731 adev->vm_manager.vm_pte_rqs[i] = in sdma_v5_0_set_vm_pte_funcs()
1734 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; in sdma_v5_0_set_vm_pte_funcs()
Dsdma_v3_0.c1704 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; in sdma_v3_0_set_vm_pte_funcs()
1707 adev->vm_manager.vm_pte_rqs[i] = in sdma_v3_0_set_vm_pte_funcs()
1710 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; in sdma_v3_0_set_vm_pte_funcs()
Damdgpu_amdkfd_gfx_v10.c933 lower_32_bits(adev->vm_manager.max_pfn - 1)); in set_vm_context_page_table_base()
935 upper_32_bits(adev->vm_manager.max_pfn - 1)); in set_vm_context_page_table_base()
Damdgpu_amdkfd.c153 .gpuvm_size = min(adev->vm_manager.max_pfn in amdgpu_amdkfd_device_init()
Dsdma_v4_0.c2529 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; in sdma_v4_0_set_vm_pte_funcs()
2535 adev->vm_manager.vm_pte_rqs[i] = in sdma_v4_0_set_vm_pte_funcs()
2538 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; in sdma_v4_0_set_vm_pte_funcs()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dradeon_vm.c62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
188 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
195 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
196 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
215 return rdev->vm_manager.active[choices[i]]; in radeon_vm_grab_id()
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Dni.c1326 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1328 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1363 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
2509 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2514 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2516 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()

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