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Searched refs:vlv_punit_read (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/
Dintel_sideband.h117 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
Dintel_sideband.c142 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr) in vlv_punit_read() function
Dintel_pm.c335 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in chv_set_memory_dvfs()
344 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in chv_set_memory_dvfs()
357 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_memory_pm5()
6140 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_wm_get_hw_state()
6153 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
6157 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in vlv_wm_get_hw_state()
6163 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
7564 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); in cherryview_rps_max_freq()
7592 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); in cherryview_rps_rpe_freq()
7602 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); in cherryview_rps_guar_freq()
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Di915_sysfs.c271 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); in gt_act_freq_mhz_show()
Di915_debugfs.c804 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); in i915_frequency_info()
1721 act_freq = vlv_punit_read(dev_priv, in i915_rps_boost_info()
/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_display_power.c1071 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) in vlv_set_power_well()
1076 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); in vlv_set_power_well()
1084 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); in vlv_set_power_well()
1118 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; in vlv_power_well_enabled()
1132 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; in vlv_power_well_enabled()
1617 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1629 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1650 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
1655 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_pipe_power_well()
1663 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); in chv_set_pipe_power_well()
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Dintel_cdclk.c476 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
558 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
562 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
640 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
644 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()