1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77990 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
8 *
9 * R8A7796 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2016-2017 Renesas Electronics Corp.
12 */
13
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16
17 #include "core.h"
18 #include "sh_pfc.h"
19
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
21
22 #define CPU_ALL_GP(fn, sfx) \
23 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
35 PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
43
44 #define CPU_ALL_NOGP(fn) \
45 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
61
62 /*
63 * F_() : just information
64 * FM() : macro for FN_xxx / xxx_MARK
65 */
66
67 /* GPSR0 */
68 #define GPSR0_17 F_(SDA4, IP7_27_24)
69 #define GPSR0_16 F_(SCL4, IP7_23_20)
70 #define GPSR0_15 F_(D15, IP7_19_16)
71 #define GPSR0_14 F_(D14, IP7_15_12)
72 #define GPSR0_13 F_(D13, IP7_11_8)
73 #define GPSR0_12 F_(D12, IP7_7_4)
74 #define GPSR0_11 F_(D11, IP7_3_0)
75 #define GPSR0_10 F_(D10, IP6_31_28)
76 #define GPSR0_9 F_(D9, IP6_27_24)
77 #define GPSR0_8 F_(D8, IP6_23_20)
78 #define GPSR0_7 F_(D7, IP6_19_16)
79 #define GPSR0_6 F_(D6, IP6_15_12)
80 #define GPSR0_5 F_(D5, IP6_11_8)
81 #define GPSR0_4 F_(D4, IP6_7_4)
82 #define GPSR0_3 F_(D3, IP6_3_0)
83 #define GPSR0_2 F_(D2, IP5_31_28)
84 #define GPSR0_1 F_(D1, IP5_27_24)
85 #define GPSR0_0 F_(D0, IP5_23_20)
86
87 /* GPSR1 */
88 #define GPSR1_22 F_(WE0_N, IP5_19_16)
89 #define GPSR1_21 F_(CS0_N, IP5_15_12)
90 #define GPSR1_20 FM(CLKOUT)
91 #define GPSR1_19 F_(A19, IP5_11_8)
92 #define GPSR1_18 F_(A18, IP5_7_4)
93 #define GPSR1_17 F_(A17, IP5_3_0)
94 #define GPSR1_16 F_(A16, IP4_31_28)
95 #define GPSR1_15 F_(A15, IP4_27_24)
96 #define GPSR1_14 F_(A14, IP4_23_20)
97 #define GPSR1_13 F_(A13, IP4_19_16)
98 #define GPSR1_12 F_(A12, IP4_15_12)
99 #define GPSR1_11 F_(A11, IP4_11_8)
100 #define GPSR1_10 F_(A10, IP4_7_4)
101 #define GPSR1_9 F_(A9, IP4_3_0)
102 #define GPSR1_8 F_(A8, IP3_31_28)
103 #define GPSR1_7 F_(A7, IP3_27_24)
104 #define GPSR1_6 F_(A6, IP3_23_20)
105 #define GPSR1_5 F_(A5, IP3_19_16)
106 #define GPSR1_4 F_(A4, IP3_15_12)
107 #define GPSR1_3 F_(A3, IP3_11_8)
108 #define GPSR1_2 F_(A2, IP3_7_4)
109 #define GPSR1_1 F_(A1, IP3_3_0)
110 #define GPSR1_0 F_(A0, IP2_31_28)
111
112 /* GPSR2 */
113 #define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
114 #define GPSR2_24 F_(RD_WR_N, IP2_23_20)
115 #define GPSR2_23 F_(RD_N, IP2_19_16)
116 #define GPSR2_22 F_(BS_N, IP2_15_12)
117 #define GPSR2_21 FM(AVB_PHY_INT)
118 #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
119 #define GPSR2_19 FM(AVB_RD3)
120 #define GPSR2_18 F_(AVB_RD2, IP1_31_28)
121 #define GPSR2_17 F_(AVB_RD1, IP1_27_24)
122 #define GPSR2_16 F_(AVB_RD0, IP1_23_20)
123 #define GPSR2_15 FM(AVB_RXC)
124 #define GPSR2_14 FM(AVB_RX_CTL)
125 #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
126 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
127 #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
128 #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
129 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
130 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
131 #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
132 #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
133 #define GPSR2_5 FM(QSPI0_SSL)
134 #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
135 #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
136 #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
137 #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
138 #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
139
140 /* GPSR3 */
141 #define GPSR3_15 F_(SD1_WP, IP11_7_4)
142 #define GPSR3_14 F_(SD1_CD, IP11_3_0)
143 #define GPSR3_13 F_(SD0_WP, IP10_31_28)
144 #define GPSR3_12 F_(SD0_CD, IP10_27_24)
145 #define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
146 #define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
147 #define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
148 #define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
149 #define GPSR3_7 F_(SD1_CMD, IP8_27_24)
150 #define GPSR3_6 F_(SD1_CLK, IP8_23_20)
151 #define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
152 #define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
153 #define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
154 #define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
155 #define GPSR3_1 F_(SD0_CMD, IP8_3_0)
156 #define GPSR3_0 F_(SD0_CLK, IP7_31_28)
157
158 /* GPSR4 */
159 #define GPSR4_10 F_(SD3_DS, IP10_23_20)
160 #define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
161 #define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
162 #define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
163 #define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
164 #define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
165 #define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
166 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
167 #define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
168 #define GPSR4_1 F_(SD3_CMD, IP9_19_16)
169 #define GPSR4_0 F_(SD3_CLK, IP9_15_12)
170
171 /* GPSR5 */
172 #define GPSR5_19 F_(MLB_DAT, IP13_23_20)
173 #define GPSR5_18 F_(MLB_SIG, IP13_19_16)
174 #define GPSR5_17 F_(MLB_CLK, IP13_15_12)
175 #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
176 #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
177 #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
178 #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
179 #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
180 #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
181 #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
182 #define GPSR5_9 F_(RX2_A, IP12_15_12)
183 #define GPSR5_8 F_(TX2_A, IP12_11_8)
184 #define GPSR5_7 F_(SCK2_A, IP12_7_4)
185 #define GPSR5_6 F_(TX1, IP12_3_0)
186 #define GPSR5_5 F_(RX1, IP11_31_28)
187 #define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
188 #define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
189 #define GPSR5_2 F_(TX0_A, IP11_15_12)
190 #define GPSR5_1 F_(RX0_A, IP11_11_8)
191 #define GPSR5_0 F_(SCK0_A, IP11_27_24)
192
193 /* GPSR6 */
194 #define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
195 #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
196 #define GPSR6_15 F_(SSI_WS6, IP15_15_12)
197 #define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
198 #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
199 #define GPSR6_12 F_(SSI_WS5, IP15_3_0)
200 #define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
201 #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
202 #define GPSR6_9 F_(USB30_OVC, IP15_31_28)
203 #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
204 #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
205 #define GPSR6_6 F_(SSI_WS349, IP14_19_16)
206 #define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
207 #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
208 #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
209 #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
210 #define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
211 #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
212
213 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
214 #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246
247 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
248 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280
281 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
282 #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314
315 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
316 #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348
349 #define PINMUX_GPSR \
350 \
351 \
352 \
353 \
354 \
355 \
356 \
357 GPSR2_25 \
358 GPSR2_24 \
359 GPSR2_23 \
360 GPSR1_22 GPSR2_22 \
361 GPSR1_21 GPSR2_21 \
362 GPSR1_20 GPSR2_20 \
363 GPSR1_19 GPSR2_19 GPSR5_19 \
364 GPSR1_18 GPSR2_18 GPSR5_18 \
365 GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
366 GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
367 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
368 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
369 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
370 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
371 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
372 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
373 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
374 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
375 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
376 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
377 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
378 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
379 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
380 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
381 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
382 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
383
384 #define PINMUX_IPSR \
385 \
386 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
387 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
388 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
389 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
390 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
391 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
392 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
393 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
394 \
395 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
396 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
397 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
398 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
399 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
400 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
401 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
402 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
403 \
404 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
405 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
406 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
407 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
408 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
409 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
410 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
411 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
412 \
413 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
414 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
415 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
416 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
417 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
418 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
419 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
420 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
421
422 /* The bit numbering in MOD_SEL fields is reversed */
423 #define REV4(f0, f1, f2, f3) f0 f2 f1 f3
424 #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7
425
426 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
427 #define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0))
428 #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
429 #define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0))
430 #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
431 #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
432 #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
433 #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
434 #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
435 #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
436 #define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
437 #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
438 #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
439 #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
440 #define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
441 #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
442 #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
443 #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
444 #define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0))
445 #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
446 #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
447 #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
448 #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
449
450 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
451 #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
452 #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
453 #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
454 #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
455 #define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0))
456 #define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0))
457 #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
458 #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
459 #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
460 #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
461 #define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0))
462 #define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0))
463 #define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0))
464 #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
465 #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
466 #define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0))
467 #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
468
469 #define PINMUX_MOD_SELS \
470 \
471 MOD_SEL0_30_29 \
472 MOD_SEL1_29 \
473 MOD_SEL0_28 MOD_SEL1_28 \
474 MOD_SEL0_27_26 \
475 MOD_SEL1_26 \
476 MOD_SEL0_25 MOD_SEL1_25 \
477 MOD_SEL0_24 MOD_SEL1_24_23_22 \
478 MOD_SEL0_23 \
479 MOD_SEL0_22 \
480 MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
481 MOD_SEL0_19_18_17 MOD_SEL1_18 \
482 MOD_SEL1_17 \
483 MOD_SEL0_16 MOD_SEL1_16 \
484 MOD_SEL0_15 MOD_SEL1_15 \
485 MOD_SEL0_14 MOD_SEL1_14_13 \
486 MOD_SEL0_13_12 \
487 MOD_SEL1_12_11 \
488 MOD_SEL0_11_10 \
489 MOD_SEL1_10_9 \
490 MOD_SEL0_9 \
491 MOD_SEL0_8 MOD_SEL1_8 \
492 MOD_SEL0_7 MOD_SEL1_7 \
493 MOD_SEL0_6_5 MOD_SEL1_6_5 \
494 MOD_SEL0_4 MOD_SEL1_4 \
495 MOD_SEL0_3 \
496 MOD_SEL0_2 \
497 MOD_SEL0_1_0
498
499 /*
500 * These pins are not able to be muxed but have other properties
501 * that can be set, such as pull-up/pull-down enable.
502 */
503 #define PINMUX_STATIC \
504 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
505 FM(AVB_TD3) \
506 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
507 FM(ASEBRK) \
508 FM(MLB_REF)
509
510 enum {
511 PINMUX_RESERVED = 0,
512
513 PINMUX_DATA_BEGIN,
514 GP_ALL(DATA),
515 PINMUX_DATA_END,
516
517 #define F_(x, y)
518 #define FM(x) FN_##x,
519 PINMUX_FUNCTION_BEGIN,
520 GP_ALL(FN),
521 PINMUX_GPSR
522 PINMUX_IPSR
523 PINMUX_MOD_SELS
524 PINMUX_FUNCTION_END,
525 #undef F_
526 #undef FM
527
528 #define F_(x, y)
529 #define FM(x) x##_MARK,
530 PINMUX_MARK_BEGIN,
531 PINMUX_GPSR
532 PINMUX_IPSR
533 PINMUX_MOD_SELS
534 PINMUX_STATIC
535 PINMUX_MARK_END,
536 #undef F_
537 #undef FM
538 };
539
540 static const u16 pinmux_data[] = {
541 PINMUX_DATA_GP_ALL(),
542
543 PINMUX_SINGLE(CLKOUT),
544 PINMUX_SINGLE(AVB_PHY_INT),
545 PINMUX_SINGLE(AVB_RD3),
546 PINMUX_SINGLE(AVB_RXC),
547 PINMUX_SINGLE(AVB_RX_CTL),
548 PINMUX_SINGLE(QSPI0_SSL),
549
550 /* IPSR0 */
551 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
552 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
553
554 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
555 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
556
557 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
558 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
559
560 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
561 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
562
563 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
564 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
565
566 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
567 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
568 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
569 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
570
571 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
572 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
573 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
574 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
575
576 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
577 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
578 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
579 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
580
581 /* IPSR1 */
582 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
583 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
584 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
585 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
586
587 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
588 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
589 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
590 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
591
592 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
593 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
594 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
595 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
596
597 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
598 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
599 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
600 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
601
602 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
603 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
604 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
605 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
606
607 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
608
609 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
610
611 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
612
613 /* IPSR2 */
614 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
615
616 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
617
618 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
619
620 PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
621 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
622 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
623 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
624 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
625 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
626
627 PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
628 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
629 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
630 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
631 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
632 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
633 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
634
635 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
636 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
637 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
638 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
639 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
640 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
641 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
642
643 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
644 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
645 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A),
646 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
647 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
648 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
649
650 PINMUX_IPSR_GPSR(IP2_31_28, A0),
651 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
652 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
653 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
654 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
655 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
656 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
657 PINMUX_IPSR_GPSR(IP2_31_28, IERX),
658 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
659
660 /* IPSR3 */
661 PINMUX_IPSR_GPSR(IP3_3_0, A1),
662 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
663 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
664 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
665 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
666 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
667 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
668 PINMUX_IPSR_GPSR(IP3_3_0, IETX),
669 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
670
671 PINMUX_IPSR_GPSR(IP3_7_4, A2),
672 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
673 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
674 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
675 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
676 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
677 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
678 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
679
680 PINMUX_IPSR_GPSR(IP3_11_8, A3),
681 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
682 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
683 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
684 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
685 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
686 PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
687 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
688
689 PINMUX_IPSR_GPSR(IP3_15_12, A4),
690 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
691 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
692 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
693 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
694 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
695 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
696
697 PINMUX_IPSR_GPSR(IP3_19_16, A5),
698 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
699 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
700 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
701 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
702 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
703 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
704
705 PINMUX_IPSR_GPSR(IP3_23_20, A6),
706 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
707 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
708 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
709 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
710
711 PINMUX_IPSR_GPSR(IP3_27_24, A7),
712 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
713 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
714 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
715 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
716
717 PINMUX_IPSR_GPSR(IP3_31_28, A8),
718 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
719 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
720 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
721 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
722 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
723 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
724 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
725
726 /* IPSR4 */
727 PINMUX_IPSR_GPSR(IP4_3_0, A9),
728 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
729 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
730 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
731 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
732 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
733 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
734
735 PINMUX_IPSR_GPSR(IP4_7_4, A10),
736 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
737 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
738 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
739 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
740 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
741 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
742 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
743
744 PINMUX_IPSR_GPSR(IP4_11_8, A11),
745 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
746 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
747 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
748 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
749 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
750 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
751
752 PINMUX_IPSR_GPSR(IP4_15_12, A12),
753 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
754 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
755 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
756 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
757 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
758 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
759
760 PINMUX_IPSR_GPSR(IP4_19_16, A13),
761 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
762 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
763 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
764 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
765 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
766 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
767
768 PINMUX_IPSR_GPSR(IP4_23_20, A14),
769 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
770 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
771 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
772 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
773 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
774 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
775
776 PINMUX_IPSR_GPSR(IP4_27_24, A15),
777 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
778 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
779 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
780 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
781 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
782 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
783
784 PINMUX_IPSR_GPSR(IP4_31_28, A16),
785 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
786 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
787 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
788 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
789 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
790 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
791
792 /* IPSR5 */
793 PINMUX_IPSR_GPSR(IP5_3_0, A17),
794 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
795 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
796 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
797 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
798 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
799
800 PINMUX_IPSR_GPSR(IP5_7_4, A18),
801 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
802 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
803 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
804 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
805 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
806 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
807
808 PINMUX_IPSR_GPSR(IP5_11_8, A19),
809 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
810 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
811 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
812 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
813 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
814 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
815
816 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
817 PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
818 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
819 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
820 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
821
822 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
823 PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
824 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
825 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
826 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
827
828 PINMUX_IPSR_GPSR(IP5_23_20, D0),
829 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
830 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
831 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
832 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
833
834 PINMUX_IPSR_GPSR(IP5_27_24, D1),
835 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
836 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
837 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
838 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
839 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
840 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
841 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
842
843 PINMUX_IPSR_GPSR(IP5_31_28, D2),
844 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
845 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
846 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
847 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
848 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
849 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
850
851 /* IPSR6 */
852 PINMUX_IPSR_GPSR(IP6_3_0, D3),
853 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
854 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
855 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
856 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
857 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
858 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
859
860 PINMUX_IPSR_GPSR(IP6_7_4, D4),
861 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
862 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
863 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
864 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
865 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
866 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
867
868 PINMUX_IPSR_GPSR(IP6_11_8, D5),
869 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
870 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
871 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
872 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
873 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
874
875 PINMUX_IPSR_GPSR(IP6_15_12, D6),
876 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
877 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
878 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
879 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
880 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
881
882 PINMUX_IPSR_GPSR(IP6_19_16, D7),
883 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
884 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
885 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
886 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
887 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
888
889 PINMUX_IPSR_GPSR(IP6_23_20, D8),
890 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
891 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
892 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
893 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
894 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
895 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
896 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
897
898 PINMUX_IPSR_GPSR(IP6_27_24, D9),
899 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
900 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
901 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
902 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
903 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
904 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
905
906 PINMUX_IPSR_GPSR(IP6_31_28, D10),
907 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
908 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
909 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
910 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
911 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
912 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
913
914 /* IPSR7 */
915 PINMUX_IPSR_GPSR(IP7_3_0, D11),
916 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
917 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
918 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
919 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
920 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
921 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
922
923 PINMUX_IPSR_GPSR(IP7_7_4, D12),
924 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
925 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
926 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
927 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
928 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
929
930 PINMUX_IPSR_GPSR(IP7_11_8, D13),
931 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
932 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
933 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
934 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
935 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
936 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
937
938 PINMUX_IPSR_GPSR(IP7_15_12, D14),
939 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
940 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
941 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
942 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
943 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
944
945 PINMUX_IPSR_GPSR(IP7_19_16, D15),
946 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
947 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
948 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
949 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
950 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
951
952 PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
953 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
954 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
955 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
956 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
957 PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
958
959 PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
960 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
961 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
962 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
963 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
964
965 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
966 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
967 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
968 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
969 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
970 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
971
972 /* IPSR8 */
973 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
974 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
975 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
976 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
977
978 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
979 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
980 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
981 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
982
983 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
984 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
985 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
986 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
987 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
988
989 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
990 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
991 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
992 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
993 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
994
995 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
996 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
997 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
998 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
999 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
1000 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
1001
1002 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
1003 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1004
1005 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
1006 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1007
1008 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
1009 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
1010
1011 /* IPSR9 */
1012 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
1013 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
1014
1015 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
1016 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
1017
1018 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
1019 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
1020
1021 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
1022 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
1023
1024 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
1025 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
1026
1027 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
1028 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
1029
1030 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
1031 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
1032
1033 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
1034 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
1035
1036 /* IPSR10 */
1037 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
1038 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
1039
1040 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
1041 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
1042
1043 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
1044 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
1045
1046 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
1047 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
1048
1049 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
1050 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
1051
1052 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
1053 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
1054
1055 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
1056 PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
1057 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
1058 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1059 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1060 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1061 PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B),
1062 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1063
1064 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
1065 PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
1066 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
1067 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1068 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1069 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1070 PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B),
1071 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1072
1073 /* IPSR11 */
1074 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
1075 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
1076 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
1077 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1078 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
1079
1080 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
1081 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
1082 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
1083 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
1084 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
1085
1086 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1087 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1088 PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A),
1089 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1090 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1091
1092 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
1093 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1094 PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A),
1095 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1096 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1097
1098 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
1099 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
1100 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
1101 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
1102 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
1103 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
1104
1105 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
1106 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
1107 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
1108 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
1109 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
1110 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
1111
1112 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
1113 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
1114 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
1115 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
1116 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1117 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
1118 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
1119
1120 PINMUX_IPSR_GPSR(IP11_31_28, RX1),
1121 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
1122 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
1123 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
1124
1125 /* IPSR12 */
1126 PINMUX_IPSR_GPSR(IP12_3_0, TX1),
1127 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
1128 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
1129 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
1130
1131 PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0),
1132 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
1133 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
1134 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
1135 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
1136 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
1137 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
1138
1139 PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0),
1140 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
1141 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
1142 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
1143 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
1144 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
1145
1146 PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0),
1147 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
1148 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
1149 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
1150 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
1151 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
1152
1153 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
1154 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
1155
1156 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
1157 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
1158 PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1),
1159
1160 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
1161 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
1162 PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1),
1163
1164 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1165 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
1166 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
1167
1168 /* IPSR13 */
1169 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1170 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
1171 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
1172 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
1173 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
1174 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
1175
1176 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1177 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
1178 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
1179 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
1180 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
1181 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
1182
1183 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
1184 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
1185 PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
1186
1187 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
1188 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
1189 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
1190 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
1191 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
1192 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
1193
1194 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
1195 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
1196 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1197 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1198 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1199 PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A),
1200
1201 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1202 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
1203 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
1204 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
1205
1206 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
1207
1208 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
1209
1210 /* IPSR14 */
1211 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
1212
1213 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
1214 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
1215 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
1216
1217 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
1218 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
1219 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
1220 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
1221
1222 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
1223 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
1224
1225 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
1226 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
1227
1228 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
1229 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
1230 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
1231 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
1232
1233 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
1234 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
1235 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
1236
1237 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
1238 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
1239 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
1240 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
1241 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
1242
1243 /* IPSR15 */
1244 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
1245 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
1246 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
1247 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
1248
1249 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
1250 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
1251 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
1252 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
1253
1254 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
1255 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
1256 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
1257 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
1258 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
1259 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
1260
1261 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
1262 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1263 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
1264 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1265 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1266 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1267 PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B),
1268
1269 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1270 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1271 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
1272 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
1273 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
1274 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
1275 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
1276
1277 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
1278
1279 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
1280 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
1281
1282 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
1283 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
1284
1285 /*
1286 * Static pins can not be muxed between different functions but
1287 * still need mark entries in the pinmux list. Add each static
1288 * pin to the list without an associated function. The sh-pfc
1289 * core will do the right thing and skip trying to mux the pin
1290 * while still applying configuration to it.
1291 */
1292 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1293 PINMUX_STATIC
1294 #undef FM
1295 };
1296
1297 /*
1298 * Pins not associated with a GPIO port.
1299 */
1300 enum {
1301 GP_ASSIGN_LAST(),
1302 NOGP_ALL(),
1303 };
1304
1305 static const struct sh_pfc_pin pinmux_pins[] = {
1306 PINMUX_GPIO_GP_ALL(),
1307 PINMUX_NOGP_ALL(),
1308 };
1309
1310 /* - AUDIO CLOCK ------------------------------------------------------------ */
1311 static const unsigned int audio_clk_a_pins[] = {
1312 /* CLK A */
1313 RCAR_GP_PIN(6, 8),
1314 };
1315
1316 static const unsigned int audio_clk_a_mux[] = {
1317 AUDIO_CLKA_MARK,
1318 };
1319
1320 static const unsigned int audio_clk_b_a_pins[] = {
1321 /* CLK B_A */
1322 RCAR_GP_PIN(5, 7),
1323 };
1324
1325 static const unsigned int audio_clk_b_a_mux[] = {
1326 AUDIO_CLKB_A_MARK,
1327 };
1328
1329 static const unsigned int audio_clk_b_b_pins[] = {
1330 /* CLK B_B */
1331 RCAR_GP_PIN(6, 7),
1332 };
1333
1334 static const unsigned int audio_clk_b_b_mux[] = {
1335 AUDIO_CLKB_B_MARK,
1336 };
1337
1338 static const unsigned int audio_clk_b_c_pins[] = {
1339 /* CLK B_C */
1340 RCAR_GP_PIN(6, 13),
1341 };
1342
1343 static const unsigned int audio_clk_b_c_mux[] = {
1344 AUDIO_CLKB_C_MARK,
1345 };
1346
1347 static const unsigned int audio_clk_c_a_pins[] = {
1348 /* CLK C_A */
1349 RCAR_GP_PIN(5, 16),
1350 };
1351
1352 static const unsigned int audio_clk_c_a_mux[] = {
1353 AUDIO_CLKC_A_MARK,
1354 };
1355
1356 static const unsigned int audio_clk_c_b_pins[] = {
1357 /* CLK C_B */
1358 RCAR_GP_PIN(6, 3),
1359 };
1360
1361 static const unsigned int audio_clk_c_b_mux[] = {
1362 AUDIO_CLKC_B_MARK,
1363 };
1364
1365 static const unsigned int audio_clk_c_c_pins[] = {
1366 /* CLK C_C */
1367 RCAR_GP_PIN(6, 14),
1368 };
1369
1370 static const unsigned int audio_clk_c_c_mux[] = {
1371 AUDIO_CLKC_C_MARK,
1372 };
1373
1374 static const unsigned int audio_clkout_a_pins[] = {
1375 /* CLKOUT_A */
1376 RCAR_GP_PIN(5, 3),
1377 };
1378
1379 static const unsigned int audio_clkout_a_mux[] = {
1380 AUDIO_CLKOUT_A_MARK,
1381 };
1382
1383 static const unsigned int audio_clkout_b_pins[] = {
1384 /* CLKOUT_B */
1385 RCAR_GP_PIN(5, 13),
1386 };
1387
1388 static const unsigned int audio_clkout_b_mux[] = {
1389 AUDIO_CLKOUT_B_MARK,
1390 };
1391
1392 static const unsigned int audio_clkout1_a_pins[] = {
1393 /* CLKOUT1_A */
1394 RCAR_GP_PIN(5, 4),
1395 };
1396
1397 static const unsigned int audio_clkout1_a_mux[] = {
1398 AUDIO_CLKOUT1_A_MARK,
1399 };
1400
1401 static const unsigned int audio_clkout1_b_pins[] = {
1402 /* CLKOUT1_B */
1403 RCAR_GP_PIN(5, 5),
1404 };
1405
1406 static const unsigned int audio_clkout1_b_mux[] = {
1407 AUDIO_CLKOUT1_B_MARK,
1408 };
1409
1410 static const unsigned int audio_clkout1_c_pins[] = {
1411 /* CLKOUT1_C */
1412 RCAR_GP_PIN(6, 7),
1413 };
1414
1415 static const unsigned int audio_clkout1_c_mux[] = {
1416 AUDIO_CLKOUT1_C_MARK,
1417 };
1418
1419 static const unsigned int audio_clkout2_a_pins[] = {
1420 /* CLKOUT2_A */
1421 RCAR_GP_PIN(5, 8),
1422 };
1423
1424 static const unsigned int audio_clkout2_a_mux[] = {
1425 AUDIO_CLKOUT2_A_MARK,
1426 };
1427
1428 static const unsigned int audio_clkout2_b_pins[] = {
1429 /* CLKOUT2_B */
1430 RCAR_GP_PIN(6, 4),
1431 };
1432
1433 static const unsigned int audio_clkout2_b_mux[] = {
1434 AUDIO_CLKOUT2_B_MARK,
1435 };
1436
1437 static const unsigned int audio_clkout2_c_pins[] = {
1438 /* CLKOUT2_C */
1439 RCAR_GP_PIN(6, 15),
1440 };
1441
1442 static const unsigned int audio_clkout2_c_mux[] = {
1443 AUDIO_CLKOUT2_C_MARK,
1444 };
1445
1446 static const unsigned int audio_clkout3_a_pins[] = {
1447 /* CLKOUT3_A */
1448 RCAR_GP_PIN(5, 9),
1449 };
1450
1451 static const unsigned int audio_clkout3_a_mux[] = {
1452 AUDIO_CLKOUT3_A_MARK,
1453 };
1454
1455 static const unsigned int audio_clkout3_b_pins[] = {
1456 /* CLKOUT3_B */
1457 RCAR_GP_PIN(5, 6),
1458 };
1459
1460 static const unsigned int audio_clkout3_b_mux[] = {
1461 AUDIO_CLKOUT3_B_MARK,
1462 };
1463
1464 static const unsigned int audio_clkout3_c_pins[] = {
1465 /* CLKOUT3_C */
1466 RCAR_GP_PIN(6, 16),
1467 };
1468
1469 static const unsigned int audio_clkout3_c_mux[] = {
1470 AUDIO_CLKOUT3_C_MARK,
1471 };
1472
1473 /* - EtherAVB --------------------------------------------------------------- */
1474 static const unsigned int avb_link_pins[] = {
1475 /* AVB_LINK */
1476 RCAR_GP_PIN(2, 23),
1477 };
1478
1479 static const unsigned int avb_link_mux[] = {
1480 AVB_LINK_MARK,
1481 };
1482
1483 static const unsigned int avb_magic_pins[] = {
1484 /* AVB_MAGIC */
1485 RCAR_GP_PIN(2, 22),
1486 };
1487
1488 static const unsigned int avb_magic_mux[] = {
1489 AVB_MAGIC_MARK,
1490 };
1491
1492 static const unsigned int avb_phy_int_pins[] = {
1493 /* AVB_PHY_INT */
1494 RCAR_GP_PIN(2, 21),
1495 };
1496
1497 static const unsigned int avb_phy_int_mux[] = {
1498 AVB_PHY_INT_MARK,
1499 };
1500
1501 static const unsigned int avb_mii_pins[] = {
1502 /*
1503 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1504 * AVB_RD1, AVB_RD2, AVB_RD3,
1505 * AVB_TXCREFCLK
1506 */
1507 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1508 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1509 RCAR_GP_PIN(2, 20),
1510 };
1511
1512 static const unsigned int avb_mii_mux[] = {
1513 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1514 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1515 AVB_TXCREFCLK_MARK,
1516 };
1517
1518 static const unsigned int avb_avtp_pps_pins[] = {
1519 /* AVB_AVTP_PPS */
1520 RCAR_GP_PIN(1, 2),
1521 };
1522
1523 static const unsigned int avb_avtp_pps_mux[] = {
1524 AVB_AVTP_PPS_MARK,
1525 };
1526
1527 static const unsigned int avb_avtp_match_a_pins[] = {
1528 /* AVB_AVTP_MATCH_A */
1529 RCAR_GP_PIN(2, 24),
1530 };
1531
1532 static const unsigned int avb_avtp_match_a_mux[] = {
1533 AVB_AVTP_MATCH_A_MARK,
1534 };
1535
1536 static const unsigned int avb_avtp_capture_a_pins[] = {
1537 /* AVB_AVTP_CAPTURE_A */
1538 RCAR_GP_PIN(2, 25),
1539 };
1540
1541 static const unsigned int avb_avtp_capture_a_mux[] = {
1542 AVB_AVTP_CAPTURE_A_MARK,
1543 };
1544
1545 /* - CAN ------------------------------------------------------------------ */
1546 static const unsigned int can0_data_pins[] = {
1547 /* TX, RX */
1548 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1549 };
1550
1551 static const unsigned int can0_data_mux[] = {
1552 CAN0_TX_MARK, CAN0_RX_MARK,
1553 };
1554
1555 static const unsigned int can1_data_pins[] = {
1556 /* TX, RX */
1557 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1558 };
1559
1560 static const unsigned int can1_data_mux[] = {
1561 CAN1_TX_MARK, CAN1_RX_MARK,
1562 };
1563
1564 /* - CAN Clock -------------------------------------------------------------- */
1565 static const unsigned int can_clk_pins[] = {
1566 /* CLK */
1567 RCAR_GP_PIN(0, 14),
1568 };
1569
1570 static const unsigned int can_clk_mux[] = {
1571 CAN_CLK_MARK,
1572 };
1573
1574 /* - CAN FD --------------------------------------------------------------- */
1575 static const unsigned int canfd0_data_pins[] = {
1576 /* TX, RX */
1577 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1578 };
1579
1580 static const unsigned int canfd0_data_mux[] = {
1581 CANFD0_TX_MARK, CANFD0_RX_MARK,
1582 };
1583
1584 static const unsigned int canfd1_data_pins[] = {
1585 /* TX, RX */
1586 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1587 };
1588
1589 static const unsigned int canfd1_data_mux[] = {
1590 CANFD1_TX_MARK, CANFD1_RX_MARK,
1591 };
1592
1593 /* - DRIF0 --------------------------------------------------------------- */
1594 static const unsigned int drif0_ctrl_a_pins[] = {
1595 /* CLK, SYNC */
1596 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
1597 };
1598
1599 static const unsigned int drif0_ctrl_a_mux[] = {
1600 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1601 };
1602
1603 static const unsigned int drif0_data0_a_pins[] = {
1604 /* D0 */
1605 RCAR_GP_PIN(5, 17),
1606 };
1607
1608 static const unsigned int drif0_data0_a_mux[] = {
1609 RIF0_D0_A_MARK,
1610 };
1611
1612 static const unsigned int drif0_data1_a_pins[] = {
1613 /* D1 */
1614 RCAR_GP_PIN(5, 18),
1615 };
1616
1617 static const unsigned int drif0_data1_a_mux[] = {
1618 RIF0_D1_A_MARK,
1619 };
1620
1621 static const unsigned int drif0_ctrl_b_pins[] = {
1622 /* CLK, SYNC */
1623 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
1624 };
1625
1626 static const unsigned int drif0_ctrl_b_mux[] = {
1627 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1628 };
1629
1630 static const unsigned int drif0_data0_b_pins[] = {
1631 /* D0 */
1632 RCAR_GP_PIN(3, 13),
1633 };
1634
1635 static const unsigned int drif0_data0_b_mux[] = {
1636 RIF0_D0_B_MARK,
1637 };
1638
1639 static const unsigned int drif0_data1_b_pins[] = {
1640 /* D1 */
1641 RCAR_GP_PIN(3, 14),
1642 };
1643
1644 static const unsigned int drif0_data1_b_mux[] = {
1645 RIF0_D1_B_MARK,
1646 };
1647
1648 /* - DRIF1 --------------------------------------------------------------- */
1649 static const unsigned int drif1_ctrl_pins[] = {
1650 /* CLK, SYNC */
1651 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
1652 };
1653
1654 static const unsigned int drif1_ctrl_mux[] = {
1655 RIF1_CLK_MARK, RIF1_SYNC_MARK,
1656 };
1657
1658 static const unsigned int drif1_data0_pins[] = {
1659 /* D0 */
1660 RCAR_GP_PIN(5, 2),
1661 };
1662
1663 static const unsigned int drif1_data0_mux[] = {
1664 RIF1_D0_MARK,
1665 };
1666
1667 static const unsigned int drif1_data1_pins[] = {
1668 /* D1 */
1669 RCAR_GP_PIN(5, 3),
1670 };
1671
1672 static const unsigned int drif1_data1_mux[] = {
1673 RIF1_D1_MARK,
1674 };
1675
1676 /* - DRIF2 --------------------------------------------------------------- */
1677 static const unsigned int drif2_ctrl_a_pins[] = {
1678 /* CLK, SYNC */
1679 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1680 };
1681
1682 static const unsigned int drif2_ctrl_a_mux[] = {
1683 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1684 };
1685
1686 static const unsigned int drif2_data0_a_pins[] = {
1687 /* D0 */
1688 RCAR_GP_PIN(2, 8),
1689 };
1690
1691 static const unsigned int drif2_data0_a_mux[] = {
1692 RIF2_D0_A_MARK,
1693 };
1694
1695 static const unsigned int drif2_data1_a_pins[] = {
1696 /* D1 */
1697 RCAR_GP_PIN(2, 9),
1698 };
1699
1700 static const unsigned int drif2_data1_a_mux[] = {
1701 RIF2_D1_A_MARK,
1702 };
1703
1704 static const unsigned int drif2_ctrl_b_pins[] = {
1705 /* CLK, SYNC */
1706 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1707 };
1708
1709 static const unsigned int drif2_ctrl_b_mux[] = {
1710 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1711 };
1712
1713 static const unsigned int drif2_data0_b_pins[] = {
1714 /* D0 */
1715 RCAR_GP_PIN(1, 6),
1716 };
1717
1718 static const unsigned int drif2_data0_b_mux[] = {
1719 RIF2_D0_B_MARK,
1720 };
1721
1722 static const unsigned int drif2_data1_b_pins[] = {
1723 /* D1 */
1724 RCAR_GP_PIN(1, 7),
1725 };
1726
1727 static const unsigned int drif2_data1_b_mux[] = {
1728 RIF2_D1_B_MARK,
1729 };
1730
1731 /* - DRIF3 --------------------------------------------------------------- */
1732 static const unsigned int drif3_ctrl_a_pins[] = {
1733 /* CLK, SYNC */
1734 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1735 };
1736
1737 static const unsigned int drif3_ctrl_a_mux[] = {
1738 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1739 };
1740
1741 static const unsigned int drif3_data0_a_pins[] = {
1742 /* D0 */
1743 RCAR_GP_PIN(2, 12),
1744 };
1745
1746 static const unsigned int drif3_data0_a_mux[] = {
1747 RIF3_D0_A_MARK,
1748 };
1749
1750 static const unsigned int drif3_data1_a_pins[] = {
1751 /* D1 */
1752 RCAR_GP_PIN(2, 13),
1753 };
1754
1755 static const unsigned int drif3_data1_a_mux[] = {
1756 RIF3_D1_A_MARK,
1757 };
1758
1759 static const unsigned int drif3_ctrl_b_pins[] = {
1760 /* CLK, SYNC */
1761 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1762 };
1763
1764 static const unsigned int drif3_ctrl_b_mux[] = {
1765 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1766 };
1767
1768 static const unsigned int drif3_data0_b_pins[] = {
1769 /* D0 */
1770 RCAR_GP_PIN(0, 10),
1771 };
1772
1773 static const unsigned int drif3_data0_b_mux[] = {
1774 RIF3_D0_B_MARK,
1775 };
1776
1777 static const unsigned int drif3_data1_b_pins[] = {
1778 /* D1 */
1779 RCAR_GP_PIN(0, 11),
1780 };
1781
1782 static const unsigned int drif3_data1_b_mux[] = {
1783 RIF3_D1_B_MARK,
1784 };
1785
1786 /* - DU --------------------------------------------------------------------- */
1787 static const unsigned int du_rgb666_pins[] = {
1788 /* R[7:2], G[7:2], B[7:2] */
1789 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1790 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1791 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1792 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1793 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1794 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1795 };
1796 static const unsigned int du_rgb666_mux[] = {
1797 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1798 DU_DR3_MARK, DU_DR2_MARK,
1799 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1800 DU_DG3_MARK, DU_DG2_MARK,
1801 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1802 DU_DB3_MARK, DU_DB2_MARK,
1803 };
1804 static const unsigned int du_rgb888_pins[] = {
1805 /* R[7:0], G[7:0], B[7:0] */
1806 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1807 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1808 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1809 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1810 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1811 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1812 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1813 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1814 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1815 };
1816 static const unsigned int du_rgb888_mux[] = {
1817 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1818 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1819 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1820 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1821 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1822 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1823 };
1824 static const unsigned int du_clk_in_0_pins[] = {
1825 /* CLKIN0 */
1826 RCAR_GP_PIN(0, 16),
1827 };
1828 static const unsigned int du_clk_in_0_mux[] = {
1829 DU_DOTCLKIN0_MARK
1830 };
1831 static const unsigned int du_clk_in_1_pins[] = {
1832 /* CLKIN1 */
1833 RCAR_GP_PIN(1, 1),
1834 };
1835 static const unsigned int du_clk_in_1_mux[] = {
1836 DU_DOTCLKIN1_MARK
1837 };
1838 static const unsigned int du_clk_out_0_pins[] = {
1839 /* CLKOUT */
1840 RCAR_GP_PIN(1, 3),
1841 };
1842 static const unsigned int du_clk_out_0_mux[] = {
1843 DU_DOTCLKOUT0_MARK
1844 };
1845 static const unsigned int du_sync_pins[] = {
1846 /* VSYNC, HSYNC */
1847 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
1848 };
1849 static const unsigned int du_sync_mux[] = {
1850 DU_VSYNC_MARK, DU_HSYNC_MARK
1851 };
1852 static const unsigned int du_disp_cde_pins[] = {
1853 /* DISP_CDE */
1854 RCAR_GP_PIN(1, 1),
1855 };
1856 static const unsigned int du_disp_cde_mux[] = {
1857 DU_DISP_CDE_MARK,
1858 };
1859 static const unsigned int du_cde_pins[] = {
1860 /* CDE */
1861 RCAR_GP_PIN(1, 0),
1862 };
1863 static const unsigned int du_cde_mux[] = {
1864 DU_CDE_MARK,
1865 };
1866 static const unsigned int du_disp_pins[] = {
1867 /* DISP */
1868 RCAR_GP_PIN(1, 2),
1869 };
1870 static const unsigned int du_disp_mux[] = {
1871 DU_DISP_MARK,
1872 };
1873
1874 /* - HSCIF0 --------------------------------------------------*/
1875 static const unsigned int hscif0_data_a_pins[] = {
1876 /* RX, TX */
1877 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1878 };
1879
1880 static const unsigned int hscif0_data_a_mux[] = {
1881 HRX0_A_MARK, HTX0_A_MARK,
1882 };
1883
1884 static const unsigned int hscif0_clk_a_pins[] = {
1885 /* SCK */
1886 RCAR_GP_PIN(5, 7),
1887 };
1888
1889 static const unsigned int hscif0_clk_a_mux[] = {
1890 HSCK0_A_MARK,
1891 };
1892
1893 static const unsigned int hscif0_ctrl_a_pins[] = {
1894 /* RTS, CTS */
1895 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1896 };
1897
1898 static const unsigned int hscif0_ctrl_a_mux[] = {
1899 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1900 };
1901
1902 static const unsigned int hscif0_data_b_pins[] = {
1903 /* RX, TX */
1904 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1905 };
1906
1907 static const unsigned int hscif0_data_b_mux[] = {
1908 HRX0_B_MARK, HTX0_B_MARK,
1909 };
1910
1911 static const unsigned int hscif0_clk_b_pins[] = {
1912 /* SCK */
1913 RCAR_GP_PIN(6, 13),
1914 };
1915
1916 static const unsigned int hscif0_clk_b_mux[] = {
1917 HSCK0_B_MARK,
1918 };
1919
1920 /* - HSCIF1 ------------------------------------------------- */
1921 static const unsigned int hscif1_data_a_pins[] = {
1922 /* RX, TX */
1923 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1924 };
1925
1926 static const unsigned int hscif1_data_a_mux[] = {
1927 HRX1_A_MARK, HTX1_A_MARK,
1928 };
1929
1930 static const unsigned int hscif1_clk_a_pins[] = {
1931 /* SCK */
1932 RCAR_GP_PIN(5, 0),
1933 };
1934
1935 static const unsigned int hscif1_clk_a_mux[] = {
1936 HSCK1_A_MARK,
1937 };
1938
1939 static const unsigned int hscif1_data_b_pins[] = {
1940 /* RX, TX */
1941 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1942 };
1943
1944 static const unsigned int hscif1_data_b_mux[] = {
1945 HRX1_B_MARK, HTX1_B_MARK,
1946 };
1947
1948 static const unsigned int hscif1_clk_b_pins[] = {
1949 /* SCK */
1950 RCAR_GP_PIN(3, 0),
1951 };
1952
1953 static const unsigned int hscif1_clk_b_mux[] = {
1954 HSCK1_B_MARK,
1955 };
1956
1957 static const unsigned int hscif1_ctrl_b_pins[] = {
1958 /* RTS, CTS */
1959 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1960 };
1961
1962 static const unsigned int hscif1_ctrl_b_mux[] = {
1963 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1964 };
1965
1966 /* - HSCIF2 ------------------------------------------------- */
1967 static const unsigned int hscif2_data_a_pins[] = {
1968 /* RX, TX */
1969 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1970 };
1971
1972 static const unsigned int hscif2_data_a_mux[] = {
1973 HRX2_A_MARK, HTX2_A_MARK,
1974 };
1975
1976 static const unsigned int hscif2_clk_a_pins[] = {
1977 /* SCK */
1978 RCAR_GP_PIN(6, 14),
1979 };
1980
1981 static const unsigned int hscif2_clk_a_mux[] = {
1982 HSCK2_A_MARK,
1983 };
1984
1985 static const unsigned int hscif2_ctrl_a_pins[] = {
1986 /* RTS, CTS */
1987 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
1988 };
1989
1990 static const unsigned int hscif2_ctrl_a_mux[] = {
1991 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1992 };
1993
1994 static const unsigned int hscif2_data_b_pins[] = {
1995 /* RX, TX */
1996 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1997 };
1998
1999 static const unsigned int hscif2_data_b_mux[] = {
2000 HRX2_B_MARK, HTX2_B_MARK,
2001 };
2002
2003 /* - HSCIF3 ------------------------------------------------*/
2004 static const unsigned int hscif3_data_a_pins[] = {
2005 /* RX, TX */
2006 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2007 };
2008
2009 static const unsigned int hscif3_data_a_mux[] = {
2010 HRX3_A_MARK, HTX3_A_MARK,
2011 };
2012
2013 static const unsigned int hscif3_data_b_pins[] = {
2014 /* RX, TX */
2015 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2016 };
2017
2018 static const unsigned int hscif3_data_b_mux[] = {
2019 HRX3_B_MARK, HTX3_B_MARK,
2020 };
2021
2022 static const unsigned int hscif3_clk_b_pins[] = {
2023 /* SCK */
2024 RCAR_GP_PIN(0, 4),
2025 };
2026
2027 static const unsigned int hscif3_clk_b_mux[] = {
2028 HSCK3_B_MARK,
2029 };
2030
2031 static const unsigned int hscif3_data_c_pins[] = {
2032 /* RX, TX */
2033 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
2034 };
2035
2036 static const unsigned int hscif3_data_c_mux[] = {
2037 HRX3_C_MARK, HTX3_C_MARK,
2038 };
2039
2040 static const unsigned int hscif3_clk_c_pins[] = {
2041 /* SCK */
2042 RCAR_GP_PIN(2, 11),
2043 };
2044
2045 static const unsigned int hscif3_clk_c_mux[] = {
2046 HSCK3_C_MARK,
2047 };
2048
2049 static const unsigned int hscif3_ctrl_c_pins[] = {
2050 /* RTS, CTS */
2051 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
2052 };
2053
2054 static const unsigned int hscif3_ctrl_c_mux[] = {
2055 HRTS3_N_C_MARK, HCTS3_N_C_MARK,
2056 };
2057
2058 static const unsigned int hscif3_data_d_pins[] = {
2059 /* RX, TX */
2060 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
2061 };
2062
2063 static const unsigned int hscif3_data_d_mux[] = {
2064 HRX3_D_MARK, HTX3_D_MARK,
2065 };
2066
2067 static const unsigned int hscif3_data_e_pins[] = {
2068 /* RX, TX */
2069 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2070 };
2071
2072 static const unsigned int hscif3_data_e_mux[] = {
2073 HRX3_E_MARK, HTX3_E_MARK,
2074 };
2075
2076 static const unsigned int hscif3_ctrl_e_pins[] = {
2077 /* RTS, CTS */
2078 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
2079 };
2080
2081 static const unsigned int hscif3_ctrl_e_mux[] = {
2082 HRTS3_N_E_MARK, HCTS3_N_E_MARK,
2083 };
2084
2085 /* - HSCIF4 -------------------------------------------------- */
2086 static const unsigned int hscif4_data_a_pins[] = {
2087 /* RX, TX */
2088 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
2089 };
2090
2091 static const unsigned int hscif4_data_a_mux[] = {
2092 HRX4_A_MARK, HTX4_A_MARK,
2093 };
2094
2095 static const unsigned int hscif4_clk_a_pins[] = {
2096 /* SCK */
2097 RCAR_GP_PIN(2, 0),
2098 };
2099
2100 static const unsigned int hscif4_clk_a_mux[] = {
2101 HSCK4_A_MARK,
2102 };
2103
2104 static const unsigned int hscif4_ctrl_a_pins[] = {
2105 /* RTS, CTS */
2106 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
2107 };
2108
2109 static const unsigned int hscif4_ctrl_a_mux[] = {
2110 HRTS4_N_A_MARK, HCTS4_N_A_MARK,
2111 };
2112
2113 static const unsigned int hscif4_data_b_pins[] = {
2114 /* RX, TX */
2115 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2116 };
2117
2118 static const unsigned int hscif4_data_b_mux[] = {
2119 HRX4_B_MARK, HTX4_B_MARK,
2120 };
2121
2122 static const unsigned int hscif4_clk_b_pins[] = {
2123 /* SCK */
2124 RCAR_GP_PIN(2, 6),
2125 };
2126
2127 static const unsigned int hscif4_clk_b_mux[] = {
2128 HSCK4_B_MARK,
2129 };
2130
2131 static const unsigned int hscif4_data_c_pins[] = {
2132 /* RX, TX */
2133 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2134 };
2135
2136 static const unsigned int hscif4_data_c_mux[] = {
2137 HRX4_C_MARK, HTX4_C_MARK,
2138 };
2139
2140 static const unsigned int hscif4_data_d_pins[] = {
2141 /* RX, TX */
2142 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2143 };
2144
2145 static const unsigned int hscif4_data_d_mux[] = {
2146 HRX4_D_MARK, HTX4_D_MARK,
2147 };
2148
2149 static const unsigned int hscif4_data_e_pins[] = {
2150 /* RX, TX */
2151 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2152 };
2153
2154 static const unsigned int hscif4_data_e_mux[] = {
2155 HRX4_E_MARK, HTX4_E_MARK,
2156 };
2157
2158 /* - I2C -------------------------------------------------------------------- */
2159 static const unsigned int i2c1_a_pins[] = {
2160 /* SCL, SDA */
2161 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2162 };
2163
2164 static const unsigned int i2c1_a_mux[] = {
2165 SCL1_A_MARK, SDA1_A_MARK,
2166 };
2167
2168 static const unsigned int i2c1_b_pins[] = {
2169 /* SCL, SDA */
2170 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2171 };
2172
2173 static const unsigned int i2c1_b_mux[] = {
2174 SCL1_B_MARK, SDA1_B_MARK,
2175 };
2176
2177 static const unsigned int i2c1_c_pins[] = {
2178 /* SCL, SDA */
2179 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
2180 };
2181
2182 static const unsigned int i2c1_c_mux[] = {
2183 SCL1_C_MARK, SDA1_C_MARK,
2184 };
2185
2186 static const unsigned int i2c1_d_pins[] = {
2187 /* SCL, SDA */
2188 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2189 };
2190
2191 static const unsigned int i2c1_d_mux[] = {
2192 SCL1_D_MARK, SDA1_D_MARK,
2193 };
2194
2195 static const unsigned int i2c2_a_pins[] = {
2196 /* SCL, SDA */
2197 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
2198 };
2199
2200 static const unsigned int i2c2_a_mux[] = {
2201 SCL2_A_MARK, SDA2_A_MARK,
2202 };
2203
2204 static const unsigned int i2c2_b_pins[] = {
2205 /* SCL, SDA */
2206 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2207 };
2208
2209 static const unsigned int i2c2_b_mux[] = {
2210 SCL2_B_MARK, SDA2_B_MARK,
2211 };
2212
2213 static const unsigned int i2c2_c_pins[] = {
2214 /* SCL, SDA */
2215 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
2216 };
2217
2218 static const unsigned int i2c2_c_mux[] = {
2219 SCL2_C_MARK, SDA2_C_MARK,
2220 };
2221
2222 static const unsigned int i2c2_d_pins[] = {
2223 /* SCL, SDA */
2224 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
2225 };
2226
2227 static const unsigned int i2c2_d_mux[] = {
2228 SCL2_D_MARK, SDA2_D_MARK,
2229 };
2230
2231 static const unsigned int i2c2_e_pins[] = {
2232 /* SCL, SDA */
2233 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
2234 };
2235
2236 static const unsigned int i2c2_e_mux[] = {
2237 SCL2_E_MARK, SDA2_E_MARK,
2238 };
2239
2240 static const unsigned int i2c4_pins[] = {
2241 /* SCL, SDA */
2242 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2243 };
2244
2245 static const unsigned int i2c4_mux[] = {
2246 SCL4_MARK, SDA4_MARK,
2247 };
2248
2249 static const unsigned int i2c5_pins[] = {
2250 /* SCL, SDA */
2251 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2252 };
2253
2254 static const unsigned int i2c5_mux[] = {
2255 SCL5_MARK, SDA5_MARK,
2256 };
2257
2258 static const unsigned int i2c6_a_pins[] = {
2259 /* SCL, SDA */
2260 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
2261 };
2262
2263 static const unsigned int i2c6_a_mux[] = {
2264 SCL6_A_MARK, SDA6_A_MARK,
2265 };
2266
2267 static const unsigned int i2c6_b_pins[] = {
2268 /* SCL, SDA */
2269 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
2270 };
2271
2272 static const unsigned int i2c6_b_mux[] = {
2273 SCL6_B_MARK, SDA6_B_MARK,
2274 };
2275
2276 static const unsigned int i2c7_a_pins[] = {
2277 /* SCL, SDA */
2278 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
2279 };
2280
2281 static const unsigned int i2c7_a_mux[] = {
2282 SCL7_A_MARK, SDA7_A_MARK,
2283 };
2284
2285 static const unsigned int i2c7_b_pins[] = {
2286 /* SCL, SDA */
2287 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
2288 };
2289
2290 static const unsigned int i2c7_b_mux[] = {
2291 SCL7_B_MARK, SDA7_B_MARK,
2292 };
2293
2294 /* - INTC-EX ---------------------------------------------------------------- */
2295 static const unsigned int intc_ex_irq0_pins[] = {
2296 /* IRQ0 */
2297 RCAR_GP_PIN(1, 0),
2298 };
2299 static const unsigned int intc_ex_irq0_mux[] = {
2300 IRQ0_MARK,
2301 };
2302 static const unsigned int intc_ex_irq1_pins[] = {
2303 /* IRQ1 */
2304 RCAR_GP_PIN(1, 1),
2305 };
2306 static const unsigned int intc_ex_irq1_mux[] = {
2307 IRQ1_MARK,
2308 };
2309 static const unsigned int intc_ex_irq2_pins[] = {
2310 /* IRQ2 */
2311 RCAR_GP_PIN(1, 2),
2312 };
2313 static const unsigned int intc_ex_irq2_mux[] = {
2314 IRQ2_MARK,
2315 };
2316 static const unsigned int intc_ex_irq3_pins[] = {
2317 /* IRQ3 */
2318 RCAR_GP_PIN(1, 9),
2319 };
2320 static const unsigned int intc_ex_irq3_mux[] = {
2321 IRQ3_MARK,
2322 };
2323 static const unsigned int intc_ex_irq4_pins[] = {
2324 /* IRQ4 */
2325 RCAR_GP_PIN(1, 10),
2326 };
2327 static const unsigned int intc_ex_irq4_mux[] = {
2328 IRQ4_MARK,
2329 };
2330 static const unsigned int intc_ex_irq5_pins[] = {
2331 /* IRQ5 */
2332 RCAR_GP_PIN(0, 7),
2333 };
2334 static const unsigned int intc_ex_irq5_mux[] = {
2335 IRQ5_MARK,
2336 };
2337
2338 /* - MSIOF0 ----------------------------------------------------------------- */
2339 static const unsigned int msiof0_clk_pins[] = {
2340 /* SCK */
2341 RCAR_GP_PIN(5, 10),
2342 };
2343
2344 static const unsigned int msiof0_clk_mux[] = {
2345 MSIOF0_SCK_MARK,
2346 };
2347
2348 static const unsigned int msiof0_sync_pins[] = {
2349 /* SYNC */
2350 RCAR_GP_PIN(5, 13),
2351 };
2352
2353 static const unsigned int msiof0_sync_mux[] = {
2354 MSIOF0_SYNC_MARK,
2355 };
2356
2357 static const unsigned int msiof0_ss1_pins[] = {
2358 /* SS1 */
2359 RCAR_GP_PIN(5, 14),
2360 };
2361
2362 static const unsigned int msiof0_ss1_mux[] = {
2363 MSIOF0_SS1_MARK,
2364 };
2365
2366 static const unsigned int msiof0_ss2_pins[] = {
2367 /* SS2 */
2368 RCAR_GP_PIN(5, 15),
2369 };
2370
2371 static const unsigned int msiof0_ss2_mux[] = {
2372 MSIOF0_SS2_MARK,
2373 };
2374
2375 static const unsigned int msiof0_txd_pins[] = {
2376 /* TXD */
2377 RCAR_GP_PIN(5, 12),
2378 };
2379
2380 static const unsigned int msiof0_txd_mux[] = {
2381 MSIOF0_TXD_MARK,
2382 };
2383
2384 static const unsigned int msiof0_rxd_pins[] = {
2385 /* RXD */
2386 RCAR_GP_PIN(5, 11),
2387 };
2388
2389 static const unsigned int msiof0_rxd_mux[] = {
2390 MSIOF0_RXD_MARK,
2391 };
2392
2393 /* - MSIOF1 ----------------------------------------------------------------- */
2394 static const unsigned int msiof1_clk_pins[] = {
2395 /* SCK */
2396 RCAR_GP_PIN(1, 19),
2397 };
2398
2399 static const unsigned int msiof1_clk_mux[] = {
2400 MSIOF1_SCK_MARK,
2401 };
2402
2403 static const unsigned int msiof1_sync_pins[] = {
2404 /* SYNC */
2405 RCAR_GP_PIN(1, 16),
2406 };
2407
2408 static const unsigned int msiof1_sync_mux[] = {
2409 MSIOF1_SYNC_MARK,
2410 };
2411
2412 static const unsigned int msiof1_ss1_pins[] = {
2413 /* SS1 */
2414 RCAR_GP_PIN(1, 14),
2415 };
2416
2417 static const unsigned int msiof1_ss1_mux[] = {
2418 MSIOF1_SS1_MARK,
2419 };
2420
2421 static const unsigned int msiof1_ss2_pins[] = {
2422 /* SS2 */
2423 RCAR_GP_PIN(1, 15),
2424 };
2425
2426 static const unsigned int msiof1_ss2_mux[] = {
2427 MSIOF1_SS2_MARK,
2428 };
2429
2430 static const unsigned int msiof1_txd_pins[] = {
2431 /* TXD */
2432 RCAR_GP_PIN(1, 18),
2433 };
2434
2435 static const unsigned int msiof1_txd_mux[] = {
2436 MSIOF1_TXD_MARK,
2437 };
2438
2439 static const unsigned int msiof1_rxd_pins[] = {
2440 /* RXD */
2441 RCAR_GP_PIN(1, 17),
2442 };
2443
2444 static const unsigned int msiof1_rxd_mux[] = {
2445 MSIOF1_RXD_MARK,
2446 };
2447
2448 /* - MSIOF2 ----------------------------------------------------------------- */
2449 static const unsigned int msiof2_clk_a_pins[] = {
2450 /* SCK */
2451 RCAR_GP_PIN(0, 8),
2452 };
2453
2454 static const unsigned int msiof2_clk_a_mux[] = {
2455 MSIOF2_SCK_A_MARK,
2456 };
2457
2458 static const unsigned int msiof2_sync_a_pins[] = {
2459 /* SYNC */
2460 RCAR_GP_PIN(0, 9),
2461 };
2462
2463 static const unsigned int msiof2_sync_a_mux[] = {
2464 MSIOF2_SYNC_A_MARK,
2465 };
2466
2467 static const unsigned int msiof2_ss1_a_pins[] = {
2468 /* SS1 */
2469 RCAR_GP_PIN(0, 15),
2470 };
2471
2472 static const unsigned int msiof2_ss1_a_mux[] = {
2473 MSIOF2_SS1_A_MARK,
2474 };
2475
2476 static const unsigned int msiof2_ss2_a_pins[] = {
2477 /* SS2 */
2478 RCAR_GP_PIN(0, 14),
2479 };
2480
2481 static const unsigned int msiof2_ss2_a_mux[] = {
2482 MSIOF2_SS2_A_MARK,
2483 };
2484
2485 static const unsigned int msiof2_txd_a_pins[] = {
2486 /* TXD */
2487 RCAR_GP_PIN(0, 11),
2488 };
2489
2490 static const unsigned int msiof2_txd_a_mux[] = {
2491 MSIOF2_TXD_A_MARK,
2492 };
2493
2494 static const unsigned int msiof2_rxd_a_pins[] = {
2495 /* RXD */
2496 RCAR_GP_PIN(0, 10),
2497 };
2498
2499 static const unsigned int msiof2_rxd_a_mux[] = {
2500 MSIOF2_RXD_A_MARK,
2501 };
2502
2503 static const unsigned int msiof2_clk_b_pins[] = {
2504 /* SCK */
2505 RCAR_GP_PIN(1, 13),
2506 };
2507
2508 static const unsigned int msiof2_clk_b_mux[] = {
2509 MSIOF2_SCK_B_MARK,
2510 };
2511
2512 static const unsigned int msiof2_sync_b_pins[] = {
2513 /* SYNC */
2514 RCAR_GP_PIN(1, 10),
2515 };
2516
2517 static const unsigned int msiof2_sync_b_mux[] = {
2518 MSIOF2_SYNC_B_MARK,
2519 };
2520
2521 static const unsigned int msiof2_ss1_b_pins[] = {
2522 /* SS1 */
2523 RCAR_GP_PIN(1, 16),
2524 };
2525
2526 static const unsigned int msiof2_ss1_b_mux[] = {
2527 MSIOF2_SS1_B_MARK,
2528 };
2529
2530 static const unsigned int msiof2_ss2_b_pins[] = {
2531 /* SS2 */
2532 RCAR_GP_PIN(1, 12),
2533 };
2534
2535 static const unsigned int msiof2_ss2_b_mux[] = {
2536 MSIOF2_SS2_B_MARK,
2537 };
2538
2539 static const unsigned int msiof2_txd_b_pins[] = {
2540 /* TXD */
2541 RCAR_GP_PIN(1, 15),
2542 };
2543
2544 static const unsigned int msiof2_txd_b_mux[] = {
2545 MSIOF2_TXD_B_MARK,
2546 };
2547
2548 static const unsigned int msiof2_rxd_b_pins[] = {
2549 /* RXD */
2550 RCAR_GP_PIN(1, 14),
2551 };
2552
2553 static const unsigned int msiof2_rxd_b_mux[] = {
2554 MSIOF2_RXD_B_MARK,
2555 };
2556
2557 /* - MSIOF3 ----------------------------------------------------------------- */
2558 static const unsigned int msiof3_clk_a_pins[] = {
2559 /* SCK */
2560 RCAR_GP_PIN(0, 0),
2561 };
2562
2563 static const unsigned int msiof3_clk_a_mux[] = {
2564 MSIOF3_SCK_A_MARK,
2565 };
2566
2567 static const unsigned int msiof3_sync_a_pins[] = {
2568 /* SYNC */
2569 RCAR_GP_PIN(0, 1),
2570 };
2571
2572 static const unsigned int msiof3_sync_a_mux[] = {
2573 MSIOF3_SYNC_A_MARK,
2574 };
2575
2576 static const unsigned int msiof3_ss1_a_pins[] = {
2577 /* SS1 */
2578 RCAR_GP_PIN(0, 15),
2579 };
2580
2581 static const unsigned int msiof3_ss1_a_mux[] = {
2582 MSIOF3_SS1_A_MARK,
2583 };
2584
2585 static const unsigned int msiof3_ss2_a_pins[] = {
2586 /* SS2 */
2587 RCAR_GP_PIN(0, 4),
2588 };
2589
2590 static const unsigned int msiof3_ss2_a_mux[] = {
2591 MSIOF3_SS2_A_MARK,
2592 };
2593
2594 static const unsigned int msiof3_txd_a_pins[] = {
2595 /* TXD */
2596 RCAR_GP_PIN(0, 3),
2597 };
2598
2599 static const unsigned int msiof3_txd_a_mux[] = {
2600 MSIOF3_TXD_A_MARK,
2601 };
2602
2603 static const unsigned int msiof3_rxd_a_pins[] = {
2604 /* RXD */
2605 RCAR_GP_PIN(0, 2),
2606 };
2607
2608 static const unsigned int msiof3_rxd_a_mux[] = {
2609 MSIOF3_RXD_A_MARK,
2610 };
2611
2612 static const unsigned int msiof3_clk_b_pins[] = {
2613 /* SCK */
2614 RCAR_GP_PIN(1, 5),
2615 };
2616
2617 static const unsigned int msiof3_clk_b_mux[] = {
2618 MSIOF3_SCK_B_MARK,
2619 };
2620
2621 static const unsigned int msiof3_sync_b_pins[] = {
2622 /* SYNC */
2623 RCAR_GP_PIN(1, 4),
2624 };
2625
2626 static const unsigned int msiof3_sync_b_mux[] = {
2627 MSIOF3_SYNC_B_MARK,
2628 };
2629
2630 static const unsigned int msiof3_ss1_b_pins[] = {
2631 /* SS1 */
2632 RCAR_GP_PIN(1, 0),
2633 };
2634
2635 static const unsigned int msiof3_ss1_b_mux[] = {
2636 MSIOF3_SS1_B_MARK,
2637 };
2638
2639 static const unsigned int msiof3_txd_b_pins[] = {
2640 /* TXD */
2641 RCAR_GP_PIN(1, 7),
2642 };
2643
2644 static const unsigned int msiof3_txd_b_mux[] = {
2645 MSIOF3_TXD_B_MARK,
2646 };
2647
2648 static const unsigned int msiof3_rxd_b_pins[] = {
2649 /* RXD */
2650 RCAR_GP_PIN(1, 6),
2651 };
2652
2653 static const unsigned int msiof3_rxd_b_mux[] = {
2654 MSIOF3_RXD_B_MARK,
2655 };
2656
2657 /* - PWM0 --------------------------------------------------------------------*/
2658 static const unsigned int pwm0_a_pins[] = {
2659 /* PWM */
2660 RCAR_GP_PIN(2, 22),
2661 };
2662
2663 static const unsigned int pwm0_a_mux[] = {
2664 PWM0_A_MARK,
2665 };
2666
2667 static const unsigned int pwm0_b_pins[] = {
2668 /* PWM */
2669 RCAR_GP_PIN(6, 3),
2670 };
2671
2672 static const unsigned int pwm0_b_mux[] = {
2673 PWM0_B_MARK,
2674 };
2675
2676 /* - PWM1 --------------------------------------------------------------------*/
2677 static const unsigned int pwm1_a_pins[] = {
2678 /* PWM */
2679 RCAR_GP_PIN(2, 23),
2680 };
2681
2682 static const unsigned int pwm1_a_mux[] = {
2683 PWM1_A_MARK,
2684 };
2685
2686 static const unsigned int pwm1_b_pins[] = {
2687 /* PWM */
2688 RCAR_GP_PIN(6, 4),
2689 };
2690
2691 static const unsigned int pwm1_b_mux[] = {
2692 PWM1_B_MARK,
2693 };
2694
2695 /* - PWM2 --------------------------------------------------------------------*/
2696 static const unsigned int pwm2_a_pins[] = {
2697 /* PWM */
2698 RCAR_GP_PIN(1, 0),
2699 };
2700
2701 static const unsigned int pwm2_a_mux[] = {
2702 PWM2_A_MARK,
2703 };
2704
2705 static const unsigned int pwm2_b_pins[] = {
2706 /* PWM */
2707 RCAR_GP_PIN(1, 4),
2708 };
2709
2710 static const unsigned int pwm2_b_mux[] = {
2711 PWM2_B_MARK,
2712 };
2713
2714 static const unsigned int pwm2_c_pins[] = {
2715 /* PWM */
2716 RCAR_GP_PIN(6, 5),
2717 };
2718
2719 static const unsigned int pwm2_c_mux[] = {
2720 PWM2_C_MARK,
2721 };
2722
2723 /* - PWM3 --------------------------------------------------------------------*/
2724 static const unsigned int pwm3_a_pins[] = {
2725 /* PWM */
2726 RCAR_GP_PIN(1, 1),
2727 };
2728
2729 static const unsigned int pwm3_a_mux[] = {
2730 PWM3_A_MARK,
2731 };
2732
2733 static const unsigned int pwm3_b_pins[] = {
2734 /* PWM */
2735 RCAR_GP_PIN(1, 5),
2736 };
2737
2738 static const unsigned int pwm3_b_mux[] = {
2739 PWM3_B_MARK,
2740 };
2741
2742 static const unsigned int pwm3_c_pins[] = {
2743 /* PWM */
2744 RCAR_GP_PIN(6, 6),
2745 };
2746
2747 static const unsigned int pwm3_c_mux[] = {
2748 PWM3_C_MARK,
2749 };
2750
2751 /* - PWM4 --------------------------------------------------------------------*/
2752 static const unsigned int pwm4_a_pins[] = {
2753 /* PWM */
2754 RCAR_GP_PIN(1, 3),
2755 };
2756
2757 static const unsigned int pwm4_a_mux[] = {
2758 PWM4_A_MARK,
2759 };
2760
2761 static const unsigned int pwm4_b_pins[] = {
2762 /* PWM */
2763 RCAR_GP_PIN(6, 7),
2764 };
2765
2766 static const unsigned int pwm4_b_mux[] = {
2767 PWM4_B_MARK,
2768 };
2769
2770 /* - PWM5 --------------------------------------------------------------------*/
2771 static const unsigned int pwm5_a_pins[] = {
2772 /* PWM */
2773 RCAR_GP_PIN(2, 24),
2774 };
2775
2776 static const unsigned int pwm5_a_mux[] = {
2777 PWM5_A_MARK,
2778 };
2779
2780 static const unsigned int pwm5_b_pins[] = {
2781 /* PWM */
2782 RCAR_GP_PIN(6, 10),
2783 };
2784
2785 static const unsigned int pwm5_b_mux[] = {
2786 PWM5_B_MARK,
2787 };
2788
2789 /* - PWM6 --------------------------------------------------------------------*/
2790 static const unsigned int pwm6_a_pins[] = {
2791 /* PWM */
2792 RCAR_GP_PIN(2, 25),
2793 };
2794
2795 static const unsigned int pwm6_a_mux[] = {
2796 PWM6_A_MARK,
2797 };
2798
2799 static const unsigned int pwm6_b_pins[] = {
2800 /* PWM */
2801 RCAR_GP_PIN(6, 11),
2802 };
2803
2804 static const unsigned int pwm6_b_mux[] = {
2805 PWM6_B_MARK,
2806 };
2807
2808 /* - SCIF0 ------------------------------------------------------------------ */
2809 static const unsigned int scif0_data_a_pins[] = {
2810 /* RX, TX */
2811 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2812 };
2813
2814 static const unsigned int scif0_data_a_mux[] = {
2815 RX0_A_MARK, TX0_A_MARK,
2816 };
2817
2818 static const unsigned int scif0_clk_a_pins[] = {
2819 /* SCK */
2820 RCAR_GP_PIN(5, 0),
2821 };
2822
2823 static const unsigned int scif0_clk_a_mux[] = {
2824 SCK0_A_MARK,
2825 };
2826
2827 static const unsigned int scif0_ctrl_a_pins[] = {
2828 /* RTS, CTS */
2829 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2830 };
2831
2832 static const unsigned int scif0_ctrl_a_mux[] = {
2833 RTS0_N_A_MARK, CTS0_N_A_MARK,
2834 };
2835
2836 static const unsigned int scif0_data_b_pins[] = {
2837 /* RX, TX */
2838 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2839 };
2840
2841 static const unsigned int scif0_data_b_mux[] = {
2842 RX0_B_MARK, TX0_B_MARK,
2843 };
2844
2845 static const unsigned int scif0_clk_b_pins[] = {
2846 /* SCK */
2847 RCAR_GP_PIN(5, 18),
2848 };
2849
2850 static const unsigned int scif0_clk_b_mux[] = {
2851 SCK0_B_MARK,
2852 };
2853
2854 /* - SCIF1 ------------------------------------------------------------------ */
2855 static const unsigned int scif1_data_pins[] = {
2856 /* RX, TX */
2857 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2858 };
2859
2860 static const unsigned int scif1_data_mux[] = {
2861 RX1_MARK, TX1_MARK,
2862 };
2863
2864 static const unsigned int scif1_clk_pins[] = {
2865 /* SCK */
2866 RCAR_GP_PIN(5, 16),
2867 };
2868
2869 static const unsigned int scif1_clk_mux[] = {
2870 SCK1_MARK,
2871 };
2872
2873 static const unsigned int scif1_ctrl_pins[] = {
2874 /* RTS, CTS */
2875 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
2876 };
2877
2878 static const unsigned int scif1_ctrl_mux[] = {
2879 RTS1_N_MARK, CTS1_N_MARK,
2880 };
2881
2882 /* - SCIF2 ------------------------------------------------------------------ */
2883 static const unsigned int scif2_data_a_pins[] = {
2884 /* RX, TX */
2885 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
2886 };
2887
2888 static const unsigned int scif2_data_a_mux[] = {
2889 RX2_A_MARK, TX2_A_MARK,
2890 };
2891
2892 static const unsigned int scif2_clk_a_pins[] = {
2893 /* SCK */
2894 RCAR_GP_PIN(5, 7),
2895 };
2896
2897 static const unsigned int scif2_clk_a_mux[] = {
2898 SCK2_A_MARK,
2899 };
2900
2901 static const unsigned int scif2_data_b_pins[] = {
2902 /* RX, TX */
2903 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
2904 };
2905
2906 static const unsigned int scif2_data_b_mux[] = {
2907 RX2_B_MARK, TX2_B_MARK,
2908 };
2909
2910 /* - SCIF3 ------------------------------------------------------------------ */
2911 static const unsigned int scif3_data_a_pins[] = {
2912 /* RX, TX */
2913 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2914 };
2915
2916 static const unsigned int scif3_data_a_mux[] = {
2917 RX3_A_MARK, TX3_A_MARK,
2918 };
2919
2920 static const unsigned int scif3_clk_a_pins[] = {
2921 /* SCK */
2922 RCAR_GP_PIN(0, 1),
2923 };
2924
2925 static const unsigned int scif3_clk_a_mux[] = {
2926 SCK3_A_MARK,
2927 };
2928
2929 static const unsigned int scif3_ctrl_a_pins[] = {
2930 /* RTS, CTS */
2931 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
2932 };
2933
2934 static const unsigned int scif3_ctrl_a_mux[] = {
2935 RTS3_N_A_MARK, CTS3_N_A_MARK,
2936 };
2937
2938 static const unsigned int scif3_data_b_pins[] = {
2939 /* RX, TX */
2940 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2941 };
2942
2943 static const unsigned int scif3_data_b_mux[] = {
2944 RX3_B_MARK, TX3_B_MARK,
2945 };
2946
2947 static const unsigned int scif3_data_c_pins[] = {
2948 /* RX, TX */
2949 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2950 };
2951
2952 static const unsigned int scif3_data_c_mux[] = {
2953 RX3_C_MARK, TX3_C_MARK,
2954 };
2955
2956 static const unsigned int scif3_clk_c_pins[] = {
2957 /* SCK */
2958 RCAR_GP_PIN(2, 24),
2959 };
2960
2961 static const unsigned int scif3_clk_c_mux[] = {
2962 SCK3_C_MARK,
2963 };
2964
2965 /* - SCIF4 ------------------------------------------------------------------ */
2966 static const unsigned int scif4_data_a_pins[] = {
2967 /* RX, TX */
2968 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2969 };
2970
2971 static const unsigned int scif4_data_a_mux[] = {
2972 RX4_A_MARK, TX4_A_MARK,
2973 };
2974
2975 static const unsigned int scif4_clk_a_pins[] = {
2976 /* SCK */
2977 RCAR_GP_PIN(1, 5),
2978 };
2979
2980 static const unsigned int scif4_clk_a_mux[] = {
2981 SCK4_A_MARK,
2982 };
2983
2984 static const unsigned int scif4_ctrl_a_pins[] = {
2985 /* RTS, CTS */
2986 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
2987 };
2988
2989 static const unsigned int scif4_ctrl_a_mux[] = {
2990 RTS4_N_A_MARK, CTS4_N_A_MARK,
2991 };
2992
2993 static const unsigned int scif4_data_b_pins[] = {
2994 /* RX, TX */
2995 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
2996 };
2997
2998 static const unsigned int scif4_data_b_mux[] = {
2999 RX4_B_MARK, TX4_B_MARK,
3000 };
3001
3002 static const unsigned int scif4_clk_b_pins[] = {
3003 /* SCK */
3004 RCAR_GP_PIN(0, 8),
3005 };
3006
3007 static const unsigned int scif4_clk_b_mux[] = {
3008 SCK4_B_MARK,
3009 };
3010
3011 static const unsigned int scif4_data_c_pins[] = {
3012 /* RX, TX */
3013 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3014 };
3015
3016 static const unsigned int scif4_data_c_mux[] = {
3017 RX4_C_MARK, TX4_C_MARK,
3018 };
3019
3020 static const unsigned int scif4_ctrl_c_pins[] = {
3021 /* RTS, CTS */
3022 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
3023 };
3024
3025 static const unsigned int scif4_ctrl_c_mux[] = {
3026 RTS4_N_C_MARK, CTS4_N_C_MARK,
3027 };
3028
3029 /* - SCIF5 ------------------------------------------------------------------ */
3030 static const unsigned int scif5_data_a_pins[] = {
3031 /* RX, TX */
3032 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
3033 };
3034
3035 static const unsigned int scif5_data_a_mux[] = {
3036 RX5_A_MARK, TX5_A_MARK,
3037 };
3038
3039 static const unsigned int scif5_clk_a_pins[] = {
3040 /* SCK */
3041 RCAR_GP_PIN(1, 13),
3042 };
3043
3044 static const unsigned int scif5_clk_a_mux[] = {
3045 SCK5_A_MARK,
3046 };
3047
3048 static const unsigned int scif5_data_b_pins[] = {
3049 /* RX, TX */
3050 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3051 };
3052
3053 static const unsigned int scif5_data_b_mux[] = {
3054 RX5_B_MARK, TX5_B_MARK,
3055 };
3056
3057 static const unsigned int scif5_data_c_pins[] = {
3058 /* RX, TX */
3059 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3060 };
3061
3062 static const unsigned int scif5_data_c_mux[] = {
3063 RX5_C_MARK, TX5_C_MARK,
3064 };
3065
3066 /* - SCIF Clock ------------------------------------------------------------- */
3067 static const unsigned int scif_clk_a_pins[] = {
3068 /* SCIF_CLK */
3069 RCAR_GP_PIN(5, 3),
3070 };
3071
3072 static const unsigned int scif_clk_a_mux[] = {
3073 SCIF_CLK_A_MARK,
3074 };
3075
3076 static const unsigned int scif_clk_b_pins[] = {
3077 /* SCIF_CLK */
3078 RCAR_GP_PIN(5, 7),
3079 };
3080
3081 static const unsigned int scif_clk_b_mux[] = {
3082 SCIF_CLK_B_MARK,
3083 };
3084
3085 /* - SDHI0 ------------------------------------------------------------------ */
3086 static const unsigned int sdhi0_data1_pins[] = {
3087 /* D0 */
3088 RCAR_GP_PIN(3, 2),
3089 };
3090
3091 static const unsigned int sdhi0_data1_mux[] = {
3092 SD0_DAT0_MARK,
3093 };
3094
3095 static const unsigned int sdhi0_data4_pins[] = {
3096 /* D[0:3] */
3097 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3098 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3099 };
3100
3101 static const unsigned int sdhi0_data4_mux[] = {
3102 SD0_DAT0_MARK, SD0_DAT1_MARK,
3103 SD0_DAT2_MARK, SD0_DAT3_MARK,
3104 };
3105
3106 static const unsigned int sdhi0_ctrl_pins[] = {
3107 /* CLK, CMD */
3108 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3109 };
3110
3111 static const unsigned int sdhi0_ctrl_mux[] = {
3112 SD0_CLK_MARK, SD0_CMD_MARK,
3113 };
3114
3115 static const unsigned int sdhi0_cd_pins[] = {
3116 /* CD */
3117 RCAR_GP_PIN(3, 12),
3118 };
3119
3120 static const unsigned int sdhi0_cd_mux[] = {
3121 SD0_CD_MARK,
3122 };
3123
3124 static const unsigned int sdhi0_wp_pins[] = {
3125 /* WP */
3126 RCAR_GP_PIN(3, 13),
3127 };
3128
3129 static const unsigned int sdhi0_wp_mux[] = {
3130 SD0_WP_MARK,
3131 };
3132
3133 /* - SDHI1 ------------------------------------------------------------------ */
3134 static const unsigned int sdhi1_data1_pins[] = {
3135 /* D0 */
3136 RCAR_GP_PIN(3, 8),
3137 };
3138
3139 static const unsigned int sdhi1_data1_mux[] = {
3140 SD1_DAT0_MARK,
3141 };
3142
3143 static const unsigned int sdhi1_data4_pins[] = {
3144 /* D[0:3] */
3145 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3146 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3147 };
3148
3149 static const unsigned int sdhi1_data4_mux[] = {
3150 SD1_DAT0_MARK, SD1_DAT1_MARK,
3151 SD1_DAT2_MARK, SD1_DAT3_MARK,
3152 };
3153
3154 static const unsigned int sdhi1_ctrl_pins[] = {
3155 /* CLK, CMD */
3156 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3157 };
3158
3159 static const unsigned int sdhi1_ctrl_mux[] = {
3160 SD1_CLK_MARK, SD1_CMD_MARK,
3161 };
3162
3163 static const unsigned int sdhi1_cd_pins[] = {
3164 /* CD */
3165 RCAR_GP_PIN(3, 14),
3166 };
3167
3168 static const unsigned int sdhi1_cd_mux[] = {
3169 SD1_CD_MARK,
3170 };
3171
3172 static const unsigned int sdhi1_wp_pins[] = {
3173 /* WP */
3174 RCAR_GP_PIN(3, 15),
3175 };
3176
3177 static const unsigned int sdhi1_wp_mux[] = {
3178 SD1_WP_MARK,
3179 };
3180
3181 /* - SDHI3 ------------------------------------------------------------------ */
3182 static const unsigned int sdhi3_data1_pins[] = {
3183 /* D0 */
3184 RCAR_GP_PIN(4, 2),
3185 };
3186
3187 static const unsigned int sdhi3_data1_mux[] = {
3188 SD3_DAT0_MARK,
3189 };
3190
3191 static const unsigned int sdhi3_data4_pins[] = {
3192 /* D[0:3] */
3193 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3194 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3195 };
3196
3197 static const unsigned int sdhi3_data4_mux[] = {
3198 SD3_DAT0_MARK, SD3_DAT1_MARK,
3199 SD3_DAT2_MARK, SD3_DAT3_MARK,
3200 };
3201
3202 static const unsigned int sdhi3_data8_pins[] = {
3203 /* D[0:7] */
3204 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3205 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3206 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
3207 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3208 };
3209
3210 static const unsigned int sdhi3_data8_mux[] = {
3211 SD3_DAT0_MARK, SD3_DAT1_MARK,
3212 SD3_DAT2_MARK, SD3_DAT3_MARK,
3213 SD3_DAT4_MARK, SD3_DAT5_MARK,
3214 SD3_DAT6_MARK, SD3_DAT7_MARK,
3215 };
3216
3217 static const unsigned int sdhi3_ctrl_pins[] = {
3218 /* CLK, CMD */
3219 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3220 };
3221
3222 static const unsigned int sdhi3_ctrl_mux[] = {
3223 SD3_CLK_MARK, SD3_CMD_MARK,
3224 };
3225
3226 static const unsigned int sdhi3_cd_pins[] = {
3227 /* CD */
3228 RCAR_GP_PIN(3, 12),
3229 };
3230
3231 static const unsigned int sdhi3_cd_mux[] = {
3232 SD3_CD_MARK,
3233 };
3234
3235 static const unsigned int sdhi3_wp_pins[] = {
3236 /* WP */
3237 RCAR_GP_PIN(3, 13),
3238 };
3239
3240 static const unsigned int sdhi3_wp_mux[] = {
3241 SD3_WP_MARK,
3242 };
3243
3244 static const unsigned int sdhi3_ds_pins[] = {
3245 /* DS */
3246 RCAR_GP_PIN(4, 10),
3247 };
3248
3249 static const unsigned int sdhi3_ds_mux[] = {
3250 SD3_DS_MARK,
3251 };
3252
3253 /* - SSI -------------------------------------------------------------------- */
3254 static const unsigned int ssi0_data_pins[] = {
3255 /* SDATA */
3256 RCAR_GP_PIN(6, 2),
3257 };
3258
3259 static const unsigned int ssi0_data_mux[] = {
3260 SSI_SDATA0_MARK,
3261 };
3262
3263 static const unsigned int ssi01239_ctrl_pins[] = {
3264 /* SCK, WS */
3265 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3266 };
3267
3268 static const unsigned int ssi01239_ctrl_mux[] = {
3269 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3270 };
3271
3272 static const unsigned int ssi1_data_pins[] = {
3273 /* SDATA */
3274 RCAR_GP_PIN(6, 3),
3275 };
3276
3277 static const unsigned int ssi1_data_mux[] = {
3278 SSI_SDATA1_MARK,
3279 };
3280
3281 static const unsigned int ssi1_ctrl_pins[] = {
3282 /* SCK, WS */
3283 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3284 };
3285
3286 static const unsigned int ssi1_ctrl_mux[] = {
3287 SSI_SCK1_MARK, SSI_WS1_MARK,
3288 };
3289
3290 static const unsigned int ssi2_data_pins[] = {
3291 /* SDATA */
3292 RCAR_GP_PIN(6, 4),
3293 };
3294
3295 static const unsigned int ssi2_data_mux[] = {
3296 SSI_SDATA2_MARK,
3297 };
3298
3299 static const unsigned int ssi2_ctrl_a_pins[] = {
3300 /* SCK, WS */
3301 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3302 };
3303
3304 static const unsigned int ssi2_ctrl_a_mux[] = {
3305 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3306 };
3307
3308 static const unsigned int ssi2_ctrl_b_pins[] = {
3309 /* SCK, WS */
3310 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3311 };
3312
3313 static const unsigned int ssi2_ctrl_b_mux[] = {
3314 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3315 };
3316
3317 static const unsigned int ssi3_data_pins[] = {
3318 /* SDATA */
3319 RCAR_GP_PIN(6, 7),
3320 };
3321
3322 static const unsigned int ssi3_data_mux[] = {
3323 SSI_SDATA3_MARK,
3324 };
3325
3326 static const unsigned int ssi349_ctrl_pins[] = {
3327 /* SCK, WS */
3328 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3329 };
3330
3331 static const unsigned int ssi349_ctrl_mux[] = {
3332 SSI_SCK349_MARK, SSI_WS349_MARK,
3333 };
3334
3335 static const unsigned int ssi4_data_pins[] = {
3336 /* SDATA */
3337 RCAR_GP_PIN(6, 10),
3338 };
3339
3340 static const unsigned int ssi4_data_mux[] = {
3341 SSI_SDATA4_MARK,
3342 };
3343
3344 static const unsigned int ssi4_ctrl_pins[] = {
3345 /* SCK, WS */
3346 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3347 };
3348
3349 static const unsigned int ssi4_ctrl_mux[] = {
3350 SSI_SCK4_MARK, SSI_WS4_MARK,
3351 };
3352
3353 static const unsigned int ssi5_data_pins[] = {
3354 /* SDATA */
3355 RCAR_GP_PIN(6, 13),
3356 };
3357
3358 static const unsigned int ssi5_data_mux[] = {
3359 SSI_SDATA5_MARK,
3360 };
3361
3362 static const unsigned int ssi5_ctrl_pins[] = {
3363 /* SCK, WS */
3364 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3365 };
3366
3367 static const unsigned int ssi5_ctrl_mux[] = {
3368 SSI_SCK5_MARK, SSI_WS5_MARK,
3369 };
3370
3371 static const unsigned int ssi6_data_pins[] = {
3372 /* SDATA */
3373 RCAR_GP_PIN(6, 16),
3374 };
3375
3376 static const unsigned int ssi6_data_mux[] = {
3377 SSI_SDATA6_MARK,
3378 };
3379
3380 static const unsigned int ssi6_ctrl_pins[] = {
3381 /* SCK, WS */
3382 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3383 };
3384
3385 static const unsigned int ssi6_ctrl_mux[] = {
3386 SSI_SCK6_MARK, SSI_WS6_MARK,
3387 };
3388
3389 static const unsigned int ssi7_data_pins[] = {
3390 /* SDATA */
3391 RCAR_GP_PIN(5, 12),
3392 };
3393
3394 static const unsigned int ssi7_data_mux[] = {
3395 SSI_SDATA7_MARK,
3396 };
3397
3398 static const unsigned int ssi78_ctrl_pins[] = {
3399 /* SCK, WS */
3400 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3401 };
3402
3403 static const unsigned int ssi78_ctrl_mux[] = {
3404 SSI_SCK78_MARK, SSI_WS78_MARK,
3405 };
3406
3407 static const unsigned int ssi8_data_pins[] = {
3408 /* SDATA */
3409 RCAR_GP_PIN(5, 13),
3410 };
3411
3412 static const unsigned int ssi8_data_mux[] = {
3413 SSI_SDATA8_MARK,
3414 };
3415
3416 static const unsigned int ssi9_data_pins[] = {
3417 /* SDATA */
3418 RCAR_GP_PIN(5, 16),
3419 };
3420
3421 static const unsigned int ssi9_data_mux[] = {
3422 SSI_SDATA9_MARK,
3423 };
3424
3425 static const unsigned int ssi9_ctrl_a_pins[] = {
3426 /* SCK, WS */
3427 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
3428 };
3429
3430 static const unsigned int ssi9_ctrl_a_mux[] = {
3431 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3432 };
3433
3434 static const unsigned int ssi9_ctrl_b_pins[] = {
3435 /* SCK, WS */
3436 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3437 };
3438
3439 static const unsigned int ssi9_ctrl_b_mux[] = {
3440 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3441 };
3442
3443 /* - TMU -------------------------------------------------------------------- */
3444 static const unsigned int tmu_tclk1_a_pins[] = {
3445 /* TCLK */
3446 RCAR_GP_PIN(3, 12),
3447 };
3448
3449 static const unsigned int tmu_tclk1_a_mux[] = {
3450 TCLK1_A_MARK,
3451 };
3452
3453 static const unsigned int tmu_tclk1_b_pins[] = {
3454 /* TCLK */
3455 RCAR_GP_PIN(5, 17),
3456 };
3457
3458 static const unsigned int tmu_tclk1_b_mux[] = {
3459 TCLK1_B_MARK,
3460 };
3461
3462 static const unsigned int tmu_tclk2_a_pins[] = {
3463 /* TCLK */
3464 RCAR_GP_PIN(3, 13),
3465 };
3466
3467 static const unsigned int tmu_tclk2_a_mux[] = {
3468 TCLK2_A_MARK,
3469 };
3470
3471 static const unsigned int tmu_tclk2_b_pins[] = {
3472 /* TCLK */
3473 RCAR_GP_PIN(5, 18),
3474 };
3475
3476 static const unsigned int tmu_tclk2_b_mux[] = {
3477 TCLK2_B_MARK,
3478 };
3479
3480 /* - USB0 ------------------------------------------------------------------- */
3481 static const unsigned int usb0_a_pins[] = {
3482 /* PWEN, OVC */
3483 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3484 };
3485
3486 static const unsigned int usb0_a_mux[] = {
3487 USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
3488 };
3489
3490 static const unsigned int usb0_b_pins[] = {
3491 /* PWEN, OVC */
3492 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3493 };
3494
3495 static const unsigned int usb0_b_mux[] = {
3496 USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
3497 };
3498
3499 static const unsigned int usb0_id_pins[] = {
3500 /* ID */
3501 RCAR_GP_PIN(5, 0)
3502 };
3503
3504 static const unsigned int usb0_id_mux[] = {
3505 USB0_ID_MARK,
3506 };
3507
3508 /* - USB30 ------------------------------------------------------------------ */
3509 static const unsigned int usb30_pins[] = {
3510 /* PWEN, OVC */
3511 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3512 };
3513
3514 static const unsigned int usb30_mux[] = {
3515 USB30_PWEN_MARK, USB30_OVC_MARK,
3516 };
3517
3518 static const unsigned int usb30_id_pins[] = {
3519 /* ID */
3520 RCAR_GP_PIN(5, 0),
3521 };
3522
3523 static const unsigned int usb30_id_mux[] = {
3524 USB3HS0_ID_MARK,
3525 };
3526
3527 /* - VIN4 ------------------------------------------------------------------- */
3528 static const unsigned int vin4_data18_a_pins[] = {
3529 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3530 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3531 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3532 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3533 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3534 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3535 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3536 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3537 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3538 };
3539
3540 static const unsigned int vin4_data18_a_mux[] = {
3541 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3542 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3543 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3544 VI4_DATA10_MARK, VI4_DATA11_MARK,
3545 VI4_DATA12_MARK, VI4_DATA13_MARK,
3546 VI4_DATA14_MARK, VI4_DATA15_MARK,
3547 VI4_DATA18_MARK, VI4_DATA19_MARK,
3548 VI4_DATA20_MARK, VI4_DATA21_MARK,
3549 VI4_DATA22_MARK, VI4_DATA23_MARK,
3550 };
3551
3552 static const union vin_data vin4_data_a_pins = {
3553 .data24 = {
3554 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3555 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3556 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3557 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3558 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3559 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3560 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3561 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3562 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3563 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3564 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3565 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3566 },
3567 };
3568
3569 static const union vin_data vin4_data_a_mux = {
3570 .data24 = {
3571 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3572 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3573 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3574 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3575 VI4_DATA8_MARK, VI4_DATA9_MARK,
3576 VI4_DATA10_MARK, VI4_DATA11_MARK,
3577 VI4_DATA12_MARK, VI4_DATA13_MARK,
3578 VI4_DATA14_MARK, VI4_DATA15_MARK,
3579 VI4_DATA16_MARK, VI4_DATA17_MARK,
3580 VI4_DATA18_MARK, VI4_DATA19_MARK,
3581 VI4_DATA20_MARK, VI4_DATA21_MARK,
3582 VI4_DATA22_MARK, VI4_DATA23_MARK,
3583 },
3584 };
3585
3586 static const unsigned int vin4_data18_b_pins[] = {
3587 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3588 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3589 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3590 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3591 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3592 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3593 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3594 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3595 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3596 };
3597
3598 static const unsigned int vin4_data18_b_mux[] = {
3599 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3600 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3601 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3602 VI4_DATA10_MARK, VI4_DATA11_MARK,
3603 VI4_DATA12_MARK, VI4_DATA13_MARK,
3604 VI4_DATA14_MARK, VI4_DATA15_MARK,
3605 VI4_DATA18_MARK, VI4_DATA19_MARK,
3606 VI4_DATA20_MARK, VI4_DATA21_MARK,
3607 VI4_DATA22_MARK, VI4_DATA23_MARK,
3608 };
3609
3610 static const union vin_data vin4_data_b_pins = {
3611 .data24 = {
3612 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3613 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3614 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3615 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3616 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3617 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3618 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3619 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3620 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3621 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3622 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3623 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3624 },
3625 };
3626
3627 static const union vin_data vin4_data_b_mux = {
3628 .data24 = {
3629 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3630 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3631 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3632 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3633 VI4_DATA8_MARK, VI4_DATA9_MARK,
3634 VI4_DATA10_MARK, VI4_DATA11_MARK,
3635 VI4_DATA12_MARK, VI4_DATA13_MARK,
3636 VI4_DATA14_MARK, VI4_DATA15_MARK,
3637 VI4_DATA16_MARK, VI4_DATA17_MARK,
3638 VI4_DATA18_MARK, VI4_DATA19_MARK,
3639 VI4_DATA20_MARK, VI4_DATA21_MARK,
3640 VI4_DATA22_MARK, VI4_DATA23_MARK,
3641 },
3642 };
3643
3644 static const unsigned int vin4_sync_pins[] = {
3645 /* HSYNC, VSYNC */
3646 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3647 };
3648
3649 static const unsigned int vin4_sync_mux[] = {
3650 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3651 };
3652
3653 static const unsigned int vin4_field_pins[] = {
3654 RCAR_GP_PIN(2, 23),
3655 };
3656
3657 static const unsigned int vin4_field_mux[] = {
3658 VI4_FIELD_MARK,
3659 };
3660
3661 static const unsigned int vin4_clkenb_pins[] = {
3662 RCAR_GP_PIN(1, 2),
3663 };
3664
3665 static const unsigned int vin4_clkenb_mux[] = {
3666 VI4_CLKENB_MARK,
3667 };
3668
3669 static const unsigned int vin4_clk_pins[] = {
3670 RCAR_GP_PIN(2, 22),
3671 };
3672
3673 static const unsigned int vin4_clk_mux[] = {
3674 VI4_CLK_MARK,
3675 };
3676
3677 /* - VIN5 ------------------------------------------------------------------- */
3678 static const union vin_data16 vin5_data_a_pins = {
3679 .data16 = {
3680 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
3681 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3682 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3683 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3684 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3685 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
3686 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
3687 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3688 },
3689 };
3690
3691 static const union vin_data16 vin5_data_a_mux = {
3692 .data16 = {
3693 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
3694 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
3695 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
3696 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
3697 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
3698 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3699 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
3700 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
3701 },
3702 };
3703
3704 static const unsigned int vin5_data8_b_pins[] = {
3705 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
3706 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12),
3707 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
3708 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3709 };
3710
3711 static const unsigned int vin5_data8_b_mux[] = {
3712 VI5_DATA0_B_MARK, VI5_DATA1_B_MARK,
3713 VI5_DATA2_B_MARK, VI5_DATA3_B_MARK,
3714 VI5_DATA4_B_MARK, VI5_DATA5_B_MARK,
3715 VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
3716 };
3717
3718 static const unsigned int vin5_sync_a_pins[] = {
3719 /* HSYNC_N, VSYNC_N */
3720 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
3721 };
3722
3723 static const unsigned int vin5_sync_a_mux[] = {
3724 VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
3725 };
3726
3727 static const unsigned int vin5_field_a_pins[] = {
3728 RCAR_GP_PIN(1, 10),
3729 };
3730
3731 static const unsigned int vin5_field_a_mux[] = {
3732 VI5_FIELD_A_MARK,
3733 };
3734
3735 static const unsigned int vin5_clkenb_a_pins[] = {
3736 RCAR_GP_PIN(0, 1),
3737 };
3738
3739 static const unsigned int vin5_clkenb_a_mux[] = {
3740 VI5_CLKENB_A_MARK,
3741 };
3742
3743 static const unsigned int vin5_clk_a_pins[] = {
3744 RCAR_GP_PIN(1, 0),
3745 };
3746
3747 static const unsigned int vin5_clk_a_mux[] = {
3748 VI5_CLK_A_MARK,
3749 };
3750
3751 static const unsigned int vin5_clk_b_pins[] = {
3752 RCAR_GP_PIN(2, 22),
3753 };
3754
3755 static const unsigned int vin5_clk_b_mux[] = {
3756 VI5_CLK_B_MARK,
3757 };
3758
3759 static const struct {
3760 struct sh_pfc_pin_group common[247];
3761 struct sh_pfc_pin_group automotive[21];
3762 } pinmux_groups = {
3763 .common = {
3764 SH_PFC_PIN_GROUP(audio_clk_a),
3765 SH_PFC_PIN_GROUP(audio_clk_b_a),
3766 SH_PFC_PIN_GROUP(audio_clk_b_b),
3767 SH_PFC_PIN_GROUP(audio_clk_b_c),
3768 SH_PFC_PIN_GROUP(audio_clk_c_a),
3769 SH_PFC_PIN_GROUP(audio_clk_c_b),
3770 SH_PFC_PIN_GROUP(audio_clk_c_c),
3771 SH_PFC_PIN_GROUP(audio_clkout_a),
3772 SH_PFC_PIN_GROUP(audio_clkout_b),
3773 SH_PFC_PIN_GROUP(audio_clkout1_a),
3774 SH_PFC_PIN_GROUP(audio_clkout1_b),
3775 SH_PFC_PIN_GROUP(audio_clkout1_c),
3776 SH_PFC_PIN_GROUP(audio_clkout2_a),
3777 SH_PFC_PIN_GROUP(audio_clkout2_b),
3778 SH_PFC_PIN_GROUP(audio_clkout2_c),
3779 SH_PFC_PIN_GROUP(audio_clkout3_a),
3780 SH_PFC_PIN_GROUP(audio_clkout3_b),
3781 SH_PFC_PIN_GROUP(audio_clkout3_c),
3782 SH_PFC_PIN_GROUP(avb_link),
3783 SH_PFC_PIN_GROUP(avb_magic),
3784 SH_PFC_PIN_GROUP(avb_phy_int),
3785 SH_PFC_PIN_GROUP(avb_mii),
3786 SH_PFC_PIN_GROUP(avb_avtp_pps),
3787 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3788 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3789 SH_PFC_PIN_GROUP(can0_data),
3790 SH_PFC_PIN_GROUP(can1_data),
3791 SH_PFC_PIN_GROUP(can_clk),
3792 SH_PFC_PIN_GROUP(canfd0_data),
3793 SH_PFC_PIN_GROUP(canfd1_data),
3794 SH_PFC_PIN_GROUP(du_rgb666),
3795 SH_PFC_PIN_GROUP(du_rgb888),
3796 SH_PFC_PIN_GROUP(du_clk_in_0),
3797 SH_PFC_PIN_GROUP(du_clk_in_1),
3798 SH_PFC_PIN_GROUP(du_clk_out_0),
3799 SH_PFC_PIN_GROUP(du_sync),
3800 SH_PFC_PIN_GROUP(du_disp_cde),
3801 SH_PFC_PIN_GROUP(du_cde),
3802 SH_PFC_PIN_GROUP(du_disp),
3803 SH_PFC_PIN_GROUP(hscif0_data_a),
3804 SH_PFC_PIN_GROUP(hscif0_clk_a),
3805 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
3806 SH_PFC_PIN_GROUP(hscif0_data_b),
3807 SH_PFC_PIN_GROUP(hscif0_clk_b),
3808 SH_PFC_PIN_GROUP(hscif1_data_a),
3809 SH_PFC_PIN_GROUP(hscif1_clk_a),
3810 SH_PFC_PIN_GROUP(hscif1_data_b),
3811 SH_PFC_PIN_GROUP(hscif1_clk_b),
3812 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3813 SH_PFC_PIN_GROUP(hscif2_data_a),
3814 SH_PFC_PIN_GROUP(hscif2_clk_a),
3815 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3816 SH_PFC_PIN_GROUP(hscif2_data_b),
3817 SH_PFC_PIN_GROUP(hscif3_data_a),
3818 SH_PFC_PIN_GROUP(hscif3_data_b),
3819 SH_PFC_PIN_GROUP(hscif3_clk_b),
3820 SH_PFC_PIN_GROUP(hscif3_data_c),
3821 SH_PFC_PIN_GROUP(hscif3_clk_c),
3822 SH_PFC_PIN_GROUP(hscif3_ctrl_c),
3823 SH_PFC_PIN_GROUP(hscif3_data_d),
3824 SH_PFC_PIN_GROUP(hscif3_data_e),
3825 SH_PFC_PIN_GROUP(hscif3_ctrl_e),
3826 SH_PFC_PIN_GROUP(hscif4_data_a),
3827 SH_PFC_PIN_GROUP(hscif4_clk_a),
3828 SH_PFC_PIN_GROUP(hscif4_ctrl_a),
3829 SH_PFC_PIN_GROUP(hscif4_data_b),
3830 SH_PFC_PIN_GROUP(hscif4_clk_b),
3831 SH_PFC_PIN_GROUP(hscif4_data_c),
3832 SH_PFC_PIN_GROUP(hscif4_data_d),
3833 SH_PFC_PIN_GROUP(hscif4_data_e),
3834 SH_PFC_PIN_GROUP(i2c1_a),
3835 SH_PFC_PIN_GROUP(i2c1_b),
3836 SH_PFC_PIN_GROUP(i2c1_c),
3837 SH_PFC_PIN_GROUP(i2c1_d),
3838 SH_PFC_PIN_GROUP(i2c2_a),
3839 SH_PFC_PIN_GROUP(i2c2_b),
3840 SH_PFC_PIN_GROUP(i2c2_c),
3841 SH_PFC_PIN_GROUP(i2c2_d),
3842 SH_PFC_PIN_GROUP(i2c2_e),
3843 SH_PFC_PIN_GROUP(i2c4),
3844 SH_PFC_PIN_GROUP(i2c5),
3845 SH_PFC_PIN_GROUP(i2c6_a),
3846 SH_PFC_PIN_GROUP(i2c6_b),
3847 SH_PFC_PIN_GROUP(i2c7_a),
3848 SH_PFC_PIN_GROUP(i2c7_b),
3849 SH_PFC_PIN_GROUP(intc_ex_irq0),
3850 SH_PFC_PIN_GROUP(intc_ex_irq1),
3851 SH_PFC_PIN_GROUP(intc_ex_irq2),
3852 SH_PFC_PIN_GROUP(intc_ex_irq3),
3853 SH_PFC_PIN_GROUP(intc_ex_irq4),
3854 SH_PFC_PIN_GROUP(intc_ex_irq5),
3855 SH_PFC_PIN_GROUP(msiof0_clk),
3856 SH_PFC_PIN_GROUP(msiof0_sync),
3857 SH_PFC_PIN_GROUP(msiof0_ss1),
3858 SH_PFC_PIN_GROUP(msiof0_ss2),
3859 SH_PFC_PIN_GROUP(msiof0_txd),
3860 SH_PFC_PIN_GROUP(msiof0_rxd),
3861 SH_PFC_PIN_GROUP(msiof1_clk),
3862 SH_PFC_PIN_GROUP(msiof1_sync),
3863 SH_PFC_PIN_GROUP(msiof1_ss1),
3864 SH_PFC_PIN_GROUP(msiof1_ss2),
3865 SH_PFC_PIN_GROUP(msiof1_txd),
3866 SH_PFC_PIN_GROUP(msiof1_rxd),
3867 SH_PFC_PIN_GROUP(msiof2_clk_a),
3868 SH_PFC_PIN_GROUP(msiof2_sync_a),
3869 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3870 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3871 SH_PFC_PIN_GROUP(msiof2_txd_a),
3872 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3873 SH_PFC_PIN_GROUP(msiof2_clk_b),
3874 SH_PFC_PIN_GROUP(msiof2_sync_b),
3875 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3876 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3877 SH_PFC_PIN_GROUP(msiof2_txd_b),
3878 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3879 SH_PFC_PIN_GROUP(msiof3_clk_a),
3880 SH_PFC_PIN_GROUP(msiof3_sync_a),
3881 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3882 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3883 SH_PFC_PIN_GROUP(msiof3_txd_a),
3884 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3885 SH_PFC_PIN_GROUP(msiof3_clk_b),
3886 SH_PFC_PIN_GROUP(msiof3_sync_b),
3887 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3888 SH_PFC_PIN_GROUP(msiof3_txd_b),
3889 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3890 SH_PFC_PIN_GROUP(pwm0_a),
3891 SH_PFC_PIN_GROUP(pwm0_b),
3892 SH_PFC_PIN_GROUP(pwm1_a),
3893 SH_PFC_PIN_GROUP(pwm1_b),
3894 SH_PFC_PIN_GROUP(pwm2_a),
3895 SH_PFC_PIN_GROUP(pwm2_b),
3896 SH_PFC_PIN_GROUP(pwm2_c),
3897 SH_PFC_PIN_GROUP(pwm3_a),
3898 SH_PFC_PIN_GROUP(pwm3_b),
3899 SH_PFC_PIN_GROUP(pwm3_c),
3900 SH_PFC_PIN_GROUP(pwm4_a),
3901 SH_PFC_PIN_GROUP(pwm4_b),
3902 SH_PFC_PIN_GROUP(pwm5_a),
3903 SH_PFC_PIN_GROUP(pwm5_b),
3904 SH_PFC_PIN_GROUP(pwm6_a),
3905 SH_PFC_PIN_GROUP(pwm6_b),
3906 SH_PFC_PIN_GROUP(scif0_data_a),
3907 SH_PFC_PIN_GROUP(scif0_clk_a),
3908 SH_PFC_PIN_GROUP(scif0_ctrl_a),
3909 SH_PFC_PIN_GROUP(scif0_data_b),
3910 SH_PFC_PIN_GROUP(scif0_clk_b),
3911 SH_PFC_PIN_GROUP(scif1_data),
3912 SH_PFC_PIN_GROUP(scif1_clk),
3913 SH_PFC_PIN_GROUP(scif1_ctrl),
3914 SH_PFC_PIN_GROUP(scif2_data_a),
3915 SH_PFC_PIN_GROUP(scif2_clk_a),
3916 SH_PFC_PIN_GROUP(scif2_data_b),
3917 SH_PFC_PIN_GROUP(scif3_data_a),
3918 SH_PFC_PIN_GROUP(scif3_clk_a),
3919 SH_PFC_PIN_GROUP(scif3_ctrl_a),
3920 SH_PFC_PIN_GROUP(scif3_data_b),
3921 SH_PFC_PIN_GROUP(scif3_data_c),
3922 SH_PFC_PIN_GROUP(scif3_clk_c),
3923 SH_PFC_PIN_GROUP(scif4_data_a),
3924 SH_PFC_PIN_GROUP(scif4_clk_a),
3925 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3926 SH_PFC_PIN_GROUP(scif4_data_b),
3927 SH_PFC_PIN_GROUP(scif4_clk_b),
3928 SH_PFC_PIN_GROUP(scif4_data_c),
3929 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3930 SH_PFC_PIN_GROUP(scif5_data_a),
3931 SH_PFC_PIN_GROUP(scif5_clk_a),
3932 SH_PFC_PIN_GROUP(scif5_data_b),
3933 SH_PFC_PIN_GROUP(scif5_data_c),
3934 SH_PFC_PIN_GROUP(scif_clk_a),
3935 SH_PFC_PIN_GROUP(scif_clk_b),
3936 SH_PFC_PIN_GROUP(sdhi0_data1),
3937 SH_PFC_PIN_GROUP(sdhi0_data4),
3938 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3939 SH_PFC_PIN_GROUP(sdhi0_cd),
3940 SH_PFC_PIN_GROUP(sdhi0_wp),
3941 SH_PFC_PIN_GROUP(sdhi1_data1),
3942 SH_PFC_PIN_GROUP(sdhi1_data4),
3943 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3944 SH_PFC_PIN_GROUP(sdhi1_cd),
3945 SH_PFC_PIN_GROUP(sdhi1_wp),
3946 SH_PFC_PIN_GROUP(sdhi3_data1),
3947 SH_PFC_PIN_GROUP(sdhi3_data4),
3948 SH_PFC_PIN_GROUP(sdhi3_data8),
3949 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3950 SH_PFC_PIN_GROUP(sdhi3_cd),
3951 SH_PFC_PIN_GROUP(sdhi3_wp),
3952 SH_PFC_PIN_GROUP(sdhi3_ds),
3953 SH_PFC_PIN_GROUP(ssi0_data),
3954 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3955 SH_PFC_PIN_GROUP(ssi1_data),
3956 SH_PFC_PIN_GROUP(ssi1_ctrl),
3957 SH_PFC_PIN_GROUP(ssi2_data),
3958 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3959 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3960 SH_PFC_PIN_GROUP(ssi3_data),
3961 SH_PFC_PIN_GROUP(ssi349_ctrl),
3962 SH_PFC_PIN_GROUP(ssi4_data),
3963 SH_PFC_PIN_GROUP(ssi4_ctrl),
3964 SH_PFC_PIN_GROUP(ssi5_data),
3965 SH_PFC_PIN_GROUP(ssi5_ctrl),
3966 SH_PFC_PIN_GROUP(ssi6_data),
3967 SH_PFC_PIN_GROUP(ssi6_ctrl),
3968 SH_PFC_PIN_GROUP(ssi7_data),
3969 SH_PFC_PIN_GROUP(ssi78_ctrl),
3970 SH_PFC_PIN_GROUP(ssi8_data),
3971 SH_PFC_PIN_GROUP(ssi9_data),
3972 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3973 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3974 SH_PFC_PIN_GROUP(tmu_tclk1_a),
3975 SH_PFC_PIN_GROUP(tmu_tclk1_b),
3976 SH_PFC_PIN_GROUP(tmu_tclk2_a),
3977 SH_PFC_PIN_GROUP(tmu_tclk2_b),
3978 SH_PFC_PIN_GROUP(usb0_a),
3979 SH_PFC_PIN_GROUP(usb0_b),
3980 SH_PFC_PIN_GROUP(usb0_id),
3981 SH_PFC_PIN_GROUP(usb30),
3982 SH_PFC_PIN_GROUP(usb30_id),
3983 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
3984 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
3985 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
3986 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
3987 SH_PFC_PIN_GROUP(vin4_data18_a),
3988 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
3989 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
3990 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
3991 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
3992 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
3993 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
3994 SH_PFC_PIN_GROUP(vin4_data18_b),
3995 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
3996 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
3997 SH_PFC_PIN_GROUP(vin4_sync),
3998 SH_PFC_PIN_GROUP(vin4_field),
3999 SH_PFC_PIN_GROUP(vin4_clkenb),
4000 SH_PFC_PIN_GROUP(vin4_clk),
4001 VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
4002 VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
4003 VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
4004 VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
4005 SH_PFC_PIN_GROUP(vin5_data8_b),
4006 SH_PFC_PIN_GROUP(vin5_sync_a),
4007 SH_PFC_PIN_GROUP(vin5_field_a),
4008 SH_PFC_PIN_GROUP(vin5_clkenb_a),
4009 SH_PFC_PIN_GROUP(vin5_clk_a),
4010 SH_PFC_PIN_GROUP(vin5_clk_b),
4011 },
4012 .automotive = {
4013 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4014 SH_PFC_PIN_GROUP(drif0_data0_a),
4015 SH_PFC_PIN_GROUP(drif0_data1_a),
4016 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4017 SH_PFC_PIN_GROUP(drif0_data0_b),
4018 SH_PFC_PIN_GROUP(drif0_data1_b),
4019 SH_PFC_PIN_GROUP(drif1_ctrl),
4020 SH_PFC_PIN_GROUP(drif1_data0),
4021 SH_PFC_PIN_GROUP(drif1_data1),
4022 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4023 SH_PFC_PIN_GROUP(drif2_data0_a),
4024 SH_PFC_PIN_GROUP(drif2_data1_a),
4025 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4026 SH_PFC_PIN_GROUP(drif2_data0_b),
4027 SH_PFC_PIN_GROUP(drif2_data1_b),
4028 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4029 SH_PFC_PIN_GROUP(drif3_data0_a),
4030 SH_PFC_PIN_GROUP(drif3_data1_a),
4031 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4032 SH_PFC_PIN_GROUP(drif3_data0_b),
4033 SH_PFC_PIN_GROUP(drif3_data1_b),
4034 }
4035 };
4036
4037 static const char * const audio_clk_groups[] = {
4038 "audio_clk_a",
4039 "audio_clk_b_a",
4040 "audio_clk_b_b",
4041 "audio_clk_b_c",
4042 "audio_clk_c_a",
4043 "audio_clk_c_b",
4044 "audio_clk_c_c",
4045 "audio_clkout_a",
4046 "audio_clkout_b",
4047 "audio_clkout1_a",
4048 "audio_clkout1_b",
4049 "audio_clkout1_c",
4050 "audio_clkout2_a",
4051 "audio_clkout2_b",
4052 "audio_clkout2_c",
4053 "audio_clkout3_a",
4054 "audio_clkout3_b",
4055 "audio_clkout3_c",
4056 };
4057
4058 static const char * const avb_groups[] = {
4059 "avb_link",
4060 "avb_magic",
4061 "avb_phy_int",
4062 "avb_mii",
4063 "avb_avtp_pps",
4064 "avb_avtp_match_a",
4065 "avb_avtp_capture_a",
4066 };
4067
4068 static const char * const can0_groups[] = {
4069 "can0_data",
4070 };
4071
4072 static const char * const can1_groups[] = {
4073 "can1_data",
4074 };
4075
4076 static const char * const can_clk_groups[] = {
4077 "can_clk",
4078 };
4079
4080 static const char * const canfd0_groups[] = {
4081 "canfd0_data",
4082 };
4083
4084 static const char * const canfd1_groups[] = {
4085 "canfd1_data",
4086 };
4087
4088 static const char * const drif0_groups[] = {
4089 "drif0_ctrl_a",
4090 "drif0_data0_a",
4091 "drif0_data1_a",
4092 "drif0_ctrl_b",
4093 "drif0_data0_b",
4094 "drif0_data1_b",
4095 };
4096
4097 static const char * const drif1_groups[] = {
4098 "drif1_ctrl",
4099 "drif1_data0",
4100 "drif1_data1",
4101 };
4102
4103 static const char * const drif2_groups[] = {
4104 "drif2_ctrl_a",
4105 "drif2_data0_a",
4106 "drif2_data1_a",
4107 "drif2_ctrl_b",
4108 "drif2_data0_b",
4109 "drif2_data1_b",
4110 };
4111
4112 static const char * const drif3_groups[] = {
4113 "drif3_ctrl_a",
4114 "drif3_data0_a",
4115 "drif3_data1_a",
4116 "drif3_ctrl_b",
4117 "drif3_data0_b",
4118 "drif3_data1_b",
4119 };
4120
4121 static const char * const du_groups[] = {
4122 "du_rgb666",
4123 "du_rgb888",
4124 "du_clk_in_0",
4125 "du_clk_in_1",
4126 "du_clk_out_0",
4127 "du_sync",
4128 "du_disp_cde",
4129 "du_cde",
4130 "du_disp",
4131 };
4132
4133 static const char * const hscif0_groups[] = {
4134 "hscif0_data_a",
4135 "hscif0_clk_a",
4136 "hscif0_ctrl_a",
4137 "hscif0_data_b",
4138 "hscif0_clk_b",
4139 };
4140
4141 static const char * const hscif1_groups[] = {
4142 "hscif1_data_a",
4143 "hscif1_clk_a",
4144 "hscif1_data_b",
4145 "hscif1_clk_b",
4146 "hscif1_ctrl_b",
4147 };
4148
4149 static const char * const hscif2_groups[] = {
4150 "hscif2_data_a",
4151 "hscif2_clk_a",
4152 "hscif2_ctrl_a",
4153 "hscif2_data_b",
4154 };
4155
4156 static const char * const hscif3_groups[] = {
4157 "hscif3_data_a",
4158 "hscif3_data_b",
4159 "hscif3_clk_b",
4160 "hscif3_data_c",
4161 "hscif3_clk_c",
4162 "hscif3_ctrl_c",
4163 "hscif3_data_d",
4164 "hscif3_data_e",
4165 "hscif3_ctrl_e",
4166 };
4167
4168 static const char * const hscif4_groups[] = {
4169 "hscif4_data_a",
4170 "hscif4_clk_a",
4171 "hscif4_ctrl_a",
4172 "hscif4_data_b",
4173 "hscif4_clk_b",
4174 "hscif4_data_c",
4175 "hscif4_data_d",
4176 "hscif4_data_e",
4177 };
4178
4179 static const char * const i2c1_groups[] = {
4180 "i2c1_a",
4181 "i2c1_b",
4182 "i2c1_c",
4183 "i2c1_d",
4184 };
4185
4186 static const char * const i2c2_groups[] = {
4187 "i2c2_a",
4188 "i2c2_b",
4189 "i2c2_c",
4190 "i2c2_d",
4191 "i2c2_e",
4192 };
4193
4194 static const char * const i2c4_groups[] = {
4195 "i2c4",
4196 };
4197
4198 static const char * const i2c5_groups[] = {
4199 "i2c5",
4200 };
4201
4202 static const char * const i2c6_groups[] = {
4203 "i2c6_a",
4204 "i2c6_b",
4205 };
4206
4207 static const char * const i2c7_groups[] = {
4208 "i2c7_a",
4209 "i2c7_b",
4210 };
4211
4212 static const char * const intc_ex_groups[] = {
4213 "intc_ex_irq0",
4214 "intc_ex_irq1",
4215 "intc_ex_irq2",
4216 "intc_ex_irq3",
4217 "intc_ex_irq4",
4218 "intc_ex_irq5",
4219 };
4220
4221 static const char * const msiof0_groups[] = {
4222 "msiof0_clk",
4223 "msiof0_sync",
4224 "msiof0_ss1",
4225 "msiof0_ss2",
4226 "msiof0_txd",
4227 "msiof0_rxd",
4228 };
4229
4230 static const char * const msiof1_groups[] = {
4231 "msiof1_clk",
4232 "msiof1_sync",
4233 "msiof1_ss1",
4234 "msiof1_ss2",
4235 "msiof1_txd",
4236 "msiof1_rxd",
4237 };
4238
4239 static const char * const msiof2_groups[] = {
4240 "msiof2_clk_a",
4241 "msiof2_sync_a",
4242 "msiof2_ss1_a",
4243 "msiof2_ss2_a",
4244 "msiof2_txd_a",
4245 "msiof2_rxd_a",
4246 "msiof2_clk_b",
4247 "msiof2_sync_b",
4248 "msiof2_ss1_b",
4249 "msiof2_ss2_b",
4250 "msiof2_txd_b",
4251 "msiof2_rxd_b",
4252 };
4253
4254 static const char * const msiof3_groups[] = {
4255 "msiof3_clk_a",
4256 "msiof3_sync_a",
4257 "msiof3_ss1_a",
4258 "msiof3_ss2_a",
4259 "msiof3_txd_a",
4260 "msiof3_rxd_a",
4261 "msiof3_clk_b",
4262 "msiof3_sync_b",
4263 "msiof3_ss1_b",
4264 "msiof3_txd_b",
4265 "msiof3_rxd_b",
4266 };
4267
4268 static const char * const pwm0_groups[] = {
4269 "pwm0_a",
4270 "pwm0_b",
4271 };
4272
4273 static const char * const pwm1_groups[] = {
4274 "pwm1_a",
4275 "pwm1_b",
4276 };
4277
4278 static const char * const pwm2_groups[] = {
4279 "pwm2_a",
4280 "pwm2_b",
4281 "pwm2_c",
4282 };
4283
4284 static const char * const pwm3_groups[] = {
4285 "pwm3_a",
4286 "pwm3_b",
4287 "pwm3_c",
4288 };
4289
4290 static const char * const pwm4_groups[] = {
4291 "pwm4_a",
4292 "pwm4_b",
4293 };
4294
4295 static const char * const pwm5_groups[] = {
4296 "pwm5_a",
4297 "pwm5_b",
4298 };
4299
4300 static const char * const pwm6_groups[] = {
4301 "pwm6_a",
4302 "pwm6_b",
4303 };
4304
4305 static const char * const scif0_groups[] = {
4306 "scif0_data_a",
4307 "scif0_clk_a",
4308 "scif0_ctrl_a",
4309 "scif0_data_b",
4310 "scif0_clk_b",
4311 };
4312
4313 static const char * const scif1_groups[] = {
4314 "scif1_data",
4315 "scif1_clk",
4316 "scif1_ctrl",
4317 };
4318
4319 static const char * const scif2_groups[] = {
4320 "scif2_data_a",
4321 "scif2_clk_a",
4322 "scif2_data_b",
4323 };
4324
4325 static const char * const scif3_groups[] = {
4326 "scif3_data_a",
4327 "scif3_clk_a",
4328 "scif3_ctrl_a",
4329 "scif3_data_b",
4330 "scif3_data_c",
4331 "scif3_clk_c",
4332 };
4333
4334 static const char * const scif4_groups[] = {
4335 "scif4_data_a",
4336 "scif4_clk_a",
4337 "scif4_ctrl_a",
4338 "scif4_data_b",
4339 "scif4_clk_b",
4340 "scif4_data_c",
4341 "scif4_ctrl_c",
4342 };
4343
4344 static const char * const scif5_groups[] = {
4345 "scif5_data_a",
4346 "scif5_clk_a",
4347 "scif5_data_b",
4348 "scif5_data_c",
4349 };
4350
4351 static const char * const scif_clk_groups[] = {
4352 "scif_clk_a",
4353 "scif_clk_b",
4354 };
4355
4356 static const char * const sdhi0_groups[] = {
4357 "sdhi0_data1",
4358 "sdhi0_data4",
4359 "sdhi0_ctrl",
4360 "sdhi0_cd",
4361 "sdhi0_wp",
4362 };
4363
4364 static const char * const sdhi1_groups[] = {
4365 "sdhi1_data1",
4366 "sdhi1_data4",
4367 "sdhi1_ctrl",
4368 "sdhi1_cd",
4369 "sdhi1_wp",
4370 };
4371
4372 static const char * const sdhi3_groups[] = {
4373 "sdhi3_data1",
4374 "sdhi3_data4",
4375 "sdhi3_data8",
4376 "sdhi3_ctrl",
4377 "sdhi3_cd",
4378 "sdhi3_wp",
4379 "sdhi3_ds",
4380 };
4381
4382 static const char * const ssi_groups[] = {
4383 "ssi0_data",
4384 "ssi01239_ctrl",
4385 "ssi1_data",
4386 "ssi1_ctrl",
4387 "ssi2_data",
4388 "ssi2_ctrl_a",
4389 "ssi2_ctrl_b",
4390 "ssi3_data",
4391 "ssi349_ctrl",
4392 "ssi4_data",
4393 "ssi4_ctrl",
4394 "ssi5_data",
4395 "ssi5_ctrl",
4396 "ssi6_data",
4397 "ssi6_ctrl",
4398 "ssi7_data",
4399 "ssi78_ctrl",
4400 "ssi8_data",
4401 "ssi9_data",
4402 "ssi9_ctrl_a",
4403 "ssi9_ctrl_b",
4404 };
4405
4406 static const char * const tmu_groups[] = {
4407 "tmu_tclk1_a",
4408 "tmu_tclk1_b",
4409 "tmu_tclk2_a",
4410 "tmu_tclk2_b",
4411 };
4412
4413 static const char * const usb0_groups[] = {
4414 "usb0_a",
4415 "usb0_b",
4416 "usb0_id",
4417 };
4418
4419 static const char * const usb30_groups[] = {
4420 "usb30",
4421 "usb30_id",
4422 };
4423
4424 static const char * const vin4_groups[] = {
4425 "vin4_data8_a",
4426 "vin4_data10_a",
4427 "vin4_data12_a",
4428 "vin4_data16_a",
4429 "vin4_data18_a",
4430 "vin4_data20_a",
4431 "vin4_data24_a",
4432 "vin4_data8_b",
4433 "vin4_data10_b",
4434 "vin4_data12_b",
4435 "vin4_data16_b",
4436 "vin4_data18_b",
4437 "vin4_data20_b",
4438 "vin4_data24_b",
4439 "vin4_sync",
4440 "vin4_field",
4441 "vin4_clkenb",
4442 "vin4_clk",
4443 };
4444
4445 static const char * const vin5_groups[] = {
4446 "vin5_data8_a",
4447 "vin5_data10_a",
4448 "vin5_data12_a",
4449 "vin5_data16_a",
4450 "vin5_data8_b",
4451 "vin5_sync_a",
4452 "vin5_field_a",
4453 "vin5_clkenb_a",
4454 "vin5_clk_a",
4455 "vin5_clk_b",
4456 };
4457
4458 static const struct {
4459 struct sh_pfc_function common[47];
4460 struct sh_pfc_function automotive[4];
4461 } pinmux_functions = {
4462 .common = {
4463 SH_PFC_FUNCTION(audio_clk),
4464 SH_PFC_FUNCTION(avb),
4465 SH_PFC_FUNCTION(can0),
4466 SH_PFC_FUNCTION(can1),
4467 SH_PFC_FUNCTION(can_clk),
4468 SH_PFC_FUNCTION(canfd0),
4469 SH_PFC_FUNCTION(canfd1),
4470 SH_PFC_FUNCTION(du),
4471 SH_PFC_FUNCTION(hscif0),
4472 SH_PFC_FUNCTION(hscif1),
4473 SH_PFC_FUNCTION(hscif2),
4474 SH_PFC_FUNCTION(hscif3),
4475 SH_PFC_FUNCTION(hscif4),
4476 SH_PFC_FUNCTION(i2c1),
4477 SH_PFC_FUNCTION(i2c2),
4478 SH_PFC_FUNCTION(i2c4),
4479 SH_PFC_FUNCTION(i2c5),
4480 SH_PFC_FUNCTION(i2c6),
4481 SH_PFC_FUNCTION(i2c7),
4482 SH_PFC_FUNCTION(intc_ex),
4483 SH_PFC_FUNCTION(msiof0),
4484 SH_PFC_FUNCTION(msiof1),
4485 SH_PFC_FUNCTION(msiof2),
4486 SH_PFC_FUNCTION(msiof3),
4487 SH_PFC_FUNCTION(pwm0),
4488 SH_PFC_FUNCTION(pwm1),
4489 SH_PFC_FUNCTION(pwm2),
4490 SH_PFC_FUNCTION(pwm3),
4491 SH_PFC_FUNCTION(pwm4),
4492 SH_PFC_FUNCTION(pwm5),
4493 SH_PFC_FUNCTION(pwm6),
4494 SH_PFC_FUNCTION(scif0),
4495 SH_PFC_FUNCTION(scif1),
4496 SH_PFC_FUNCTION(scif2),
4497 SH_PFC_FUNCTION(scif3),
4498 SH_PFC_FUNCTION(scif4),
4499 SH_PFC_FUNCTION(scif5),
4500 SH_PFC_FUNCTION(scif_clk),
4501 SH_PFC_FUNCTION(sdhi0),
4502 SH_PFC_FUNCTION(sdhi1),
4503 SH_PFC_FUNCTION(sdhi3),
4504 SH_PFC_FUNCTION(ssi),
4505 SH_PFC_FUNCTION(tmu),
4506 SH_PFC_FUNCTION(usb0),
4507 SH_PFC_FUNCTION(usb30),
4508 SH_PFC_FUNCTION(vin4),
4509 SH_PFC_FUNCTION(vin5),
4510 },
4511 .automotive = {
4512 SH_PFC_FUNCTION(drif0),
4513 SH_PFC_FUNCTION(drif1),
4514 SH_PFC_FUNCTION(drif2),
4515 SH_PFC_FUNCTION(drif3),
4516 }
4517 };
4518
4519 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4520 #define F_(x, y) FN_##y
4521 #define FM(x) FN_##x
4522 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
4523 0, 0,
4524 0, 0,
4525 0, 0,
4526 0, 0,
4527 0, 0,
4528 0, 0,
4529 0, 0,
4530 0, 0,
4531 0, 0,
4532 0, 0,
4533 0, 0,
4534 0, 0,
4535 0, 0,
4536 0, 0,
4537 GP_0_17_FN, GPSR0_17,
4538 GP_0_16_FN, GPSR0_16,
4539 GP_0_15_FN, GPSR0_15,
4540 GP_0_14_FN, GPSR0_14,
4541 GP_0_13_FN, GPSR0_13,
4542 GP_0_12_FN, GPSR0_12,
4543 GP_0_11_FN, GPSR0_11,
4544 GP_0_10_FN, GPSR0_10,
4545 GP_0_9_FN, GPSR0_9,
4546 GP_0_8_FN, GPSR0_8,
4547 GP_0_7_FN, GPSR0_7,
4548 GP_0_6_FN, GPSR0_6,
4549 GP_0_5_FN, GPSR0_5,
4550 GP_0_4_FN, GPSR0_4,
4551 GP_0_3_FN, GPSR0_3,
4552 GP_0_2_FN, GPSR0_2,
4553 GP_0_1_FN, GPSR0_1,
4554 GP_0_0_FN, GPSR0_0, ))
4555 },
4556 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4557 0, 0,
4558 0, 0,
4559 0, 0,
4560 0, 0,
4561 0, 0,
4562 0, 0,
4563 0, 0,
4564 0, 0,
4565 0, 0,
4566 GP_1_22_FN, GPSR1_22,
4567 GP_1_21_FN, GPSR1_21,
4568 GP_1_20_FN, GPSR1_20,
4569 GP_1_19_FN, GPSR1_19,
4570 GP_1_18_FN, GPSR1_18,
4571 GP_1_17_FN, GPSR1_17,
4572 GP_1_16_FN, GPSR1_16,
4573 GP_1_15_FN, GPSR1_15,
4574 GP_1_14_FN, GPSR1_14,
4575 GP_1_13_FN, GPSR1_13,
4576 GP_1_12_FN, GPSR1_12,
4577 GP_1_11_FN, GPSR1_11,
4578 GP_1_10_FN, GPSR1_10,
4579 GP_1_9_FN, GPSR1_9,
4580 GP_1_8_FN, GPSR1_8,
4581 GP_1_7_FN, GPSR1_7,
4582 GP_1_6_FN, GPSR1_6,
4583 GP_1_5_FN, GPSR1_5,
4584 GP_1_4_FN, GPSR1_4,
4585 GP_1_3_FN, GPSR1_3,
4586 GP_1_2_FN, GPSR1_2,
4587 GP_1_1_FN, GPSR1_1,
4588 GP_1_0_FN, GPSR1_0, ))
4589 },
4590 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4591 0, 0,
4592 0, 0,
4593 0, 0,
4594 0, 0,
4595 0, 0,
4596 0, 0,
4597 GP_2_25_FN, GPSR2_25,
4598 GP_2_24_FN, GPSR2_24,
4599 GP_2_23_FN, GPSR2_23,
4600 GP_2_22_FN, GPSR2_22,
4601 GP_2_21_FN, GPSR2_21,
4602 GP_2_20_FN, GPSR2_20,
4603 GP_2_19_FN, GPSR2_19,
4604 GP_2_18_FN, GPSR2_18,
4605 GP_2_17_FN, GPSR2_17,
4606 GP_2_16_FN, GPSR2_16,
4607 GP_2_15_FN, GPSR2_15,
4608 GP_2_14_FN, GPSR2_14,
4609 GP_2_13_FN, GPSR2_13,
4610 GP_2_12_FN, GPSR2_12,
4611 GP_2_11_FN, GPSR2_11,
4612 GP_2_10_FN, GPSR2_10,
4613 GP_2_9_FN, GPSR2_9,
4614 GP_2_8_FN, GPSR2_8,
4615 GP_2_7_FN, GPSR2_7,
4616 GP_2_6_FN, GPSR2_6,
4617 GP_2_5_FN, GPSR2_5,
4618 GP_2_4_FN, GPSR2_4,
4619 GP_2_3_FN, GPSR2_3,
4620 GP_2_2_FN, GPSR2_2,
4621 GP_2_1_FN, GPSR2_1,
4622 GP_2_0_FN, GPSR2_0, ))
4623 },
4624 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
4625 0, 0,
4626 0, 0,
4627 0, 0,
4628 0, 0,
4629 0, 0,
4630 0, 0,
4631 0, 0,
4632 0, 0,
4633 0, 0,
4634 0, 0,
4635 0, 0,
4636 0, 0,
4637 0, 0,
4638 0, 0,
4639 0, 0,
4640 0, 0,
4641 GP_3_15_FN, GPSR3_15,
4642 GP_3_14_FN, GPSR3_14,
4643 GP_3_13_FN, GPSR3_13,
4644 GP_3_12_FN, GPSR3_12,
4645 GP_3_11_FN, GPSR3_11,
4646 GP_3_10_FN, GPSR3_10,
4647 GP_3_9_FN, GPSR3_9,
4648 GP_3_8_FN, GPSR3_8,
4649 GP_3_7_FN, GPSR3_7,
4650 GP_3_6_FN, GPSR3_6,
4651 GP_3_5_FN, GPSR3_5,
4652 GP_3_4_FN, GPSR3_4,
4653 GP_3_3_FN, GPSR3_3,
4654 GP_3_2_FN, GPSR3_2,
4655 GP_3_1_FN, GPSR3_1,
4656 GP_3_0_FN, GPSR3_0, ))
4657 },
4658 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
4659 0, 0,
4660 0, 0,
4661 0, 0,
4662 0, 0,
4663 0, 0,
4664 0, 0,
4665 0, 0,
4666 0, 0,
4667 0, 0,
4668 0, 0,
4669 0, 0,
4670 0, 0,
4671 0, 0,
4672 0, 0,
4673 0, 0,
4674 0, 0,
4675 0, 0,
4676 0, 0,
4677 0, 0,
4678 0, 0,
4679 0, 0,
4680 GP_4_10_FN, GPSR4_10,
4681 GP_4_9_FN, GPSR4_9,
4682 GP_4_8_FN, GPSR4_8,
4683 GP_4_7_FN, GPSR4_7,
4684 GP_4_6_FN, GPSR4_6,
4685 GP_4_5_FN, GPSR4_5,
4686 GP_4_4_FN, GPSR4_4,
4687 GP_4_3_FN, GPSR4_3,
4688 GP_4_2_FN, GPSR4_2,
4689 GP_4_1_FN, GPSR4_1,
4690 GP_4_0_FN, GPSR4_0, ))
4691 },
4692 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4693 0, 0,
4694 0, 0,
4695 0, 0,
4696 0, 0,
4697 0, 0,
4698 0, 0,
4699 0, 0,
4700 0, 0,
4701 0, 0,
4702 0, 0,
4703 0, 0,
4704 0, 0,
4705 GP_5_19_FN, GPSR5_19,
4706 GP_5_18_FN, GPSR5_18,
4707 GP_5_17_FN, GPSR5_17,
4708 GP_5_16_FN, GPSR5_16,
4709 GP_5_15_FN, GPSR5_15,
4710 GP_5_14_FN, GPSR5_14,
4711 GP_5_13_FN, GPSR5_13,
4712 GP_5_12_FN, GPSR5_12,
4713 GP_5_11_FN, GPSR5_11,
4714 GP_5_10_FN, GPSR5_10,
4715 GP_5_9_FN, GPSR5_9,
4716 GP_5_8_FN, GPSR5_8,
4717 GP_5_7_FN, GPSR5_7,
4718 GP_5_6_FN, GPSR5_6,
4719 GP_5_5_FN, GPSR5_5,
4720 GP_5_4_FN, GPSR5_4,
4721 GP_5_3_FN, GPSR5_3,
4722 GP_5_2_FN, GPSR5_2,
4723 GP_5_1_FN, GPSR5_1,
4724 GP_5_0_FN, GPSR5_0, ))
4725 },
4726 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4727 0, 0,
4728 0, 0,
4729 0, 0,
4730 0, 0,
4731 0, 0,
4732 0, 0,
4733 0, 0,
4734 0, 0,
4735 0, 0,
4736 0, 0,
4737 0, 0,
4738 0, 0,
4739 0, 0,
4740 0, 0,
4741 GP_6_17_FN, GPSR6_17,
4742 GP_6_16_FN, GPSR6_16,
4743 GP_6_15_FN, GPSR6_15,
4744 GP_6_14_FN, GPSR6_14,
4745 GP_6_13_FN, GPSR6_13,
4746 GP_6_12_FN, GPSR6_12,
4747 GP_6_11_FN, GPSR6_11,
4748 GP_6_10_FN, GPSR6_10,
4749 GP_6_9_FN, GPSR6_9,
4750 GP_6_8_FN, GPSR6_8,
4751 GP_6_7_FN, GPSR6_7,
4752 GP_6_6_FN, GPSR6_6,
4753 GP_6_5_FN, GPSR6_5,
4754 GP_6_4_FN, GPSR6_4,
4755 GP_6_3_FN, GPSR6_3,
4756 GP_6_2_FN, GPSR6_2,
4757 GP_6_1_FN, GPSR6_1,
4758 GP_6_0_FN, GPSR6_0, ))
4759 },
4760 #undef F_
4761 #undef FM
4762
4763 #define F_(x, y) x,
4764 #define FM(x) FN_##x,
4765 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
4766 IP0_31_28
4767 IP0_27_24
4768 IP0_23_20
4769 IP0_19_16
4770 IP0_15_12
4771 IP0_11_8
4772 IP0_7_4
4773 IP0_3_0 ))
4774 },
4775 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
4776 IP1_31_28
4777 IP1_27_24
4778 IP1_23_20
4779 IP1_19_16
4780 IP1_15_12
4781 IP1_11_8
4782 IP1_7_4
4783 IP1_3_0 ))
4784 },
4785 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
4786 IP2_31_28
4787 IP2_27_24
4788 IP2_23_20
4789 IP2_19_16
4790 IP2_15_12
4791 IP2_11_8
4792 IP2_7_4
4793 IP2_3_0 ))
4794 },
4795 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
4796 IP3_31_28
4797 IP3_27_24
4798 IP3_23_20
4799 IP3_19_16
4800 IP3_15_12
4801 IP3_11_8
4802 IP3_7_4
4803 IP3_3_0 ))
4804 },
4805 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
4806 IP4_31_28
4807 IP4_27_24
4808 IP4_23_20
4809 IP4_19_16
4810 IP4_15_12
4811 IP4_11_8
4812 IP4_7_4
4813 IP4_3_0 ))
4814 },
4815 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
4816 IP5_31_28
4817 IP5_27_24
4818 IP5_23_20
4819 IP5_19_16
4820 IP5_15_12
4821 IP5_11_8
4822 IP5_7_4
4823 IP5_3_0 ))
4824 },
4825 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
4826 IP6_31_28
4827 IP6_27_24
4828 IP6_23_20
4829 IP6_19_16
4830 IP6_15_12
4831 IP6_11_8
4832 IP6_7_4
4833 IP6_3_0 ))
4834 },
4835 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
4836 IP7_31_28
4837 IP7_27_24
4838 IP7_23_20
4839 IP7_19_16
4840 IP7_15_12
4841 IP7_11_8
4842 IP7_7_4
4843 IP7_3_0 ))
4844 },
4845 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
4846 IP8_31_28
4847 IP8_27_24
4848 IP8_23_20
4849 IP8_19_16
4850 IP8_15_12
4851 IP8_11_8
4852 IP8_7_4
4853 IP8_3_0 ))
4854 },
4855 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
4856 IP9_31_28
4857 IP9_27_24
4858 IP9_23_20
4859 IP9_19_16
4860 IP9_15_12
4861 IP9_11_8
4862 IP9_7_4
4863 IP9_3_0 ))
4864 },
4865 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
4866 IP10_31_28
4867 IP10_27_24
4868 IP10_23_20
4869 IP10_19_16
4870 IP10_15_12
4871 IP10_11_8
4872 IP10_7_4
4873 IP10_3_0 ))
4874 },
4875 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
4876 IP11_31_28
4877 IP11_27_24
4878 IP11_23_20
4879 IP11_19_16
4880 IP11_15_12
4881 IP11_11_8
4882 IP11_7_4
4883 IP11_3_0 ))
4884 },
4885 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
4886 IP12_31_28
4887 IP12_27_24
4888 IP12_23_20
4889 IP12_19_16
4890 IP12_15_12
4891 IP12_11_8
4892 IP12_7_4
4893 IP12_3_0 ))
4894 },
4895 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
4896 IP13_31_28
4897 IP13_27_24
4898 IP13_23_20
4899 IP13_19_16
4900 IP13_15_12
4901 IP13_11_8
4902 IP13_7_4
4903 IP13_3_0 ))
4904 },
4905 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
4906 IP14_31_28
4907 IP14_27_24
4908 IP14_23_20
4909 IP14_19_16
4910 IP14_15_12
4911 IP14_11_8
4912 IP14_7_4
4913 IP14_3_0 ))
4914 },
4915 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
4916 IP15_31_28
4917 IP15_27_24
4918 IP15_23_20
4919 IP15_19_16
4920 IP15_15_12
4921 IP15_11_8
4922 IP15_7_4
4923 IP15_3_0 ))
4924 },
4925 #undef F_
4926 #undef FM
4927
4928 #define F_(x, y) x,
4929 #define FM(x) FN_##x,
4930 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4931 GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
4932 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
4933 GROUP(
4934 /* RESERVED 31 */
4935 0, 0,
4936 MOD_SEL0_30_29
4937 MOD_SEL0_28
4938 MOD_SEL0_27_26
4939 MOD_SEL0_25
4940 MOD_SEL0_24
4941 MOD_SEL0_23
4942 MOD_SEL0_22
4943 MOD_SEL0_21_20
4944 MOD_SEL0_19_18_17
4945 MOD_SEL0_16
4946 MOD_SEL0_15
4947 MOD_SEL0_14
4948 MOD_SEL0_13_12
4949 MOD_SEL0_11_10
4950 MOD_SEL0_9
4951 MOD_SEL0_8
4952 MOD_SEL0_7
4953 MOD_SEL0_6_5
4954 MOD_SEL0_4
4955 MOD_SEL0_3
4956 MOD_SEL0_2
4957 MOD_SEL0_1_0 ))
4958 },
4959 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4960 GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
4961 2, 2, 2, 1, 1, 2, 1, 4),
4962 GROUP(
4963 /* RESERVED 31, 30 */
4964 0, 0, 0, 0,
4965 MOD_SEL1_29
4966 MOD_SEL1_28
4967 /* RESERVED 27 */
4968 0, 0,
4969 MOD_SEL1_26
4970 MOD_SEL1_25
4971 MOD_SEL1_24_23_22
4972 MOD_SEL1_21_20_19
4973 MOD_SEL1_18
4974 MOD_SEL1_17
4975 MOD_SEL1_16
4976 MOD_SEL1_15
4977 MOD_SEL1_14_13
4978 MOD_SEL1_12_11
4979 MOD_SEL1_10_9
4980 MOD_SEL1_8
4981 MOD_SEL1_7
4982 MOD_SEL1_6_5
4983 MOD_SEL1_4
4984 /* RESERVED 3, 2, 1, 0 */
4985 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
4986 },
4987 { },
4988 };
4989
4990 enum ioctrl_regs {
4991 POCCTRL0,
4992 TDSELCTRL,
4993 };
4994
4995 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
4996 [POCCTRL0] = { 0xe6060380, },
4997 [TDSELCTRL] = { 0xe60603c0, },
4998 { /* sentinel */ },
4999 };
5000
r8a77990_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)5001 static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5002 u32 *pocctrl)
5003 {
5004 int bit = -EINVAL;
5005
5006 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
5007
5008 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5009 bit = pin & 0x1f;
5010
5011 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
5012 bit = (pin & 0x1f) + 19;
5013
5014 return bit;
5015 }
5016
5017 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5018 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5019 [0] = RCAR_GP_PIN(2, 23), /* RD# */
5020 [1] = RCAR_GP_PIN(2, 22), /* BS# */
5021 [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
5022 [3] = PIN_AVB_MDC, /* AVB_MDC */
5023 [4] = PIN_AVB_MDIO, /* AVB_MDIO */
5024 [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
5025 [6] = PIN_AVB_TD3, /* AVB_TD3 */
5026 [7] = PIN_AVB_TD2, /* AVB_TD2 */
5027 [8] = PIN_AVB_TD1, /* AVB_TD1 */
5028 [9] = PIN_AVB_TD0, /* AVB_TD0 */
5029 [10] = PIN_AVB_TXC, /* AVB_TXC */
5030 [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5031 [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
5032 [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
5033 [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
5034 [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */
5035 [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */
5036 [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */
5037 [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */
5038 [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */
5039 [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */
5040 [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */
5041 [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */
5042 [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */
5043 [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */
5044 [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */
5045 [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */
5046 [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */
5047 [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */
5048 [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */
5049 [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */
5050 [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */
5051 } },
5052 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5053 [0] = RCAR_GP_PIN(0, 4), /* D4 */
5054 [1] = RCAR_GP_PIN(0, 3), /* D3 */
5055 [2] = RCAR_GP_PIN(0, 2), /* D2 */
5056 [3] = RCAR_GP_PIN(0, 1), /* D1 */
5057 [4] = RCAR_GP_PIN(0, 0), /* D0 */
5058 [5] = RCAR_GP_PIN(1, 22), /* WE0# */
5059 [6] = RCAR_GP_PIN(1, 21), /* CS0# */
5060 [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */
5061 [8] = RCAR_GP_PIN(1, 19), /* A19 */
5062 [9] = RCAR_GP_PIN(1, 18), /* A18 */
5063 [10] = RCAR_GP_PIN(1, 17), /* A17 */
5064 [11] = RCAR_GP_PIN(1, 16), /* A16 */
5065 [12] = RCAR_GP_PIN(1, 15), /* A15 */
5066 [13] = RCAR_GP_PIN(1, 14), /* A14 */
5067 [14] = RCAR_GP_PIN(1, 13), /* A13 */
5068 [15] = RCAR_GP_PIN(1, 12), /* A12 */
5069 [16] = RCAR_GP_PIN(1, 11), /* A11 */
5070 [17] = RCAR_GP_PIN(1, 10), /* A10 */
5071 [18] = RCAR_GP_PIN(1, 9), /* A9 */
5072 [19] = RCAR_GP_PIN(1, 8), /* A8 */
5073 [20] = RCAR_GP_PIN(1, 7), /* A7 */
5074 [21] = RCAR_GP_PIN(1, 6), /* A6 */
5075 [22] = RCAR_GP_PIN(1, 5), /* A5 */
5076 [23] = RCAR_GP_PIN(1, 4), /* A4 */
5077 [24] = RCAR_GP_PIN(1, 3), /* A3 */
5078 [25] = RCAR_GP_PIN(1, 2), /* A2 */
5079 [26] = RCAR_GP_PIN(1, 1), /* A1 */
5080 [27] = RCAR_GP_PIN(1, 0), /* A0 */
5081 [28] = SH_PFC_PIN_NONE,
5082 [29] = SH_PFC_PIN_NONE,
5083 [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
5084 [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
5085 } },
5086 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5087 [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5088 [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5089 [2] = PIN_ASEBRK, /* ASEBRK */
5090 [3] = SH_PFC_PIN_NONE,
5091 [4] = PIN_TDI, /* TDI */
5092 [5] = PIN_TMS, /* TMS */
5093 [6] = PIN_TCK, /* TCK */
5094 [7] = PIN_TRST_N, /* TRST# */
5095 [8] = SH_PFC_PIN_NONE,
5096 [9] = SH_PFC_PIN_NONE,
5097 [10] = SH_PFC_PIN_NONE,
5098 [11] = SH_PFC_PIN_NONE,
5099 [12] = SH_PFC_PIN_NONE,
5100 [13] = SH_PFC_PIN_NONE,
5101 [14] = SH_PFC_PIN_NONE,
5102 [15] = PIN_FSCLKST_N, /* FSCLKST# */
5103 [16] = RCAR_GP_PIN(0, 17), /* SDA4 */
5104 [17] = RCAR_GP_PIN(0, 16), /* SCL4 */
5105 [18] = SH_PFC_PIN_NONE,
5106 [19] = SH_PFC_PIN_NONE,
5107 [20] = PIN_PRESETOUT_N, /* PRESETOUT# */
5108 [21] = RCAR_GP_PIN(0, 15), /* D15 */
5109 [22] = RCAR_GP_PIN(0, 14), /* D14 */
5110 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5111 [24] = RCAR_GP_PIN(0, 12), /* D12 */
5112 [25] = RCAR_GP_PIN(0, 11), /* D11 */
5113 [26] = RCAR_GP_PIN(0, 10), /* D10 */
5114 [27] = RCAR_GP_PIN(0, 9), /* D9 */
5115 [28] = RCAR_GP_PIN(0, 8), /* D8 */
5116 [29] = RCAR_GP_PIN(0, 7), /* D7 */
5117 [30] = RCAR_GP_PIN(0, 6), /* D6 */
5118 [31] = RCAR_GP_PIN(0, 5), /* D5 */
5119 } },
5120 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5121 [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
5122 [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
5123 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
5124 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */
5125 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */
5126 [5] = SH_PFC_PIN_NONE,
5127 [6] = SH_PFC_PIN_NONE,
5128 [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5129 [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5130 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5131 [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5132 [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */
5133 [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */
5134 [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */
5135 [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */
5136 [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */
5137 [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */
5138 [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */
5139 [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */
5140 [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */
5141 [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */
5142 [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */
5143 [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5144 [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5145 [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5146 [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5147 [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5148 [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5149 [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5150 [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5151 [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5152 [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5153 } },
5154 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5155 [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */
5156 [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5157 [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5158 [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5159 [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5160 [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5161 [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5162 [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5163 [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5164 [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5165 [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5166 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */
5167 [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */
5168 [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5169 [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5170 [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5171 [16] = PIN_MLB_REF, /* MLB_REF */
5172 [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
5173 [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
5174 [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
5175 [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */
5176 [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */
5177 [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
5178 [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
5179 [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */
5180 [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */
5181 [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */
5182 [27] = RCAR_GP_PIN(5, 9), /* RX2_A */
5183 [28] = RCAR_GP_PIN(5, 8), /* TX2_A */
5184 [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */
5185 [30] = RCAR_GP_PIN(5, 6), /* TX1 */
5186 [31] = RCAR_GP_PIN(5, 5), /* RX1 */
5187 } },
5188 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5189 [0] = SH_PFC_PIN_NONE,
5190 [1] = SH_PFC_PIN_NONE,
5191 [2] = SH_PFC_PIN_NONE,
5192 [3] = SH_PFC_PIN_NONE,
5193 [4] = SH_PFC_PIN_NONE,
5194 [5] = SH_PFC_PIN_NONE,
5195 [6] = SH_PFC_PIN_NONE,
5196 [7] = SH_PFC_PIN_NONE,
5197 [8] = SH_PFC_PIN_NONE,
5198 [9] = SH_PFC_PIN_NONE,
5199 [10] = SH_PFC_PIN_NONE,
5200 [11] = SH_PFC_PIN_NONE,
5201 [12] = SH_PFC_PIN_NONE,
5202 [13] = SH_PFC_PIN_NONE,
5203 [14] = SH_PFC_PIN_NONE,
5204 [15] = SH_PFC_PIN_NONE,
5205 [16] = SH_PFC_PIN_NONE,
5206 [17] = SH_PFC_PIN_NONE,
5207 [18] = SH_PFC_PIN_NONE,
5208 [19] = SH_PFC_PIN_NONE,
5209 [20] = SH_PFC_PIN_NONE,
5210 [21] = SH_PFC_PIN_NONE,
5211 [22] = SH_PFC_PIN_NONE,
5212 [23] = SH_PFC_PIN_NONE,
5213 [24] = SH_PFC_PIN_NONE,
5214 [25] = SH_PFC_PIN_NONE,
5215 [26] = SH_PFC_PIN_NONE,
5216 [27] = SH_PFC_PIN_NONE,
5217 [28] = SH_PFC_PIN_NONE,
5218 [29] = SH_PFC_PIN_NONE,
5219 [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
5220 [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
5221 } },
5222 { /* sentinel */ },
5223 };
5224
r8a77990_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)5225 static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
5226 unsigned int pin)
5227 {
5228 const struct pinmux_bias_reg *reg;
5229 unsigned int bit;
5230
5231 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5232 if (!reg)
5233 return PIN_CONFIG_BIAS_DISABLE;
5234
5235 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5236 return PIN_CONFIG_BIAS_DISABLE;
5237 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5238 return PIN_CONFIG_BIAS_PULL_UP;
5239 else
5240 return PIN_CONFIG_BIAS_PULL_DOWN;
5241 }
5242
r8a77990_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)5243 static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5244 unsigned int bias)
5245 {
5246 const struct pinmux_bias_reg *reg;
5247 u32 enable, updown;
5248 unsigned int bit;
5249
5250 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5251 if (!reg)
5252 return;
5253
5254 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5255 if (bias != PIN_CONFIG_BIAS_DISABLE)
5256 enable |= BIT(bit);
5257
5258 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5259 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5260 updown |= BIT(bit);
5261
5262 sh_pfc_write(pfc, reg->pud, updown);
5263 sh_pfc_write(pfc, reg->puen, enable);
5264 }
5265
5266 static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
5267 .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
5268 .get_bias = r8a77990_pinmux_get_bias,
5269 .set_bias = r8a77990_pinmux_set_bias,
5270 };
5271
5272 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
5273 const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
5274 .name = "r8a774c0_pfc",
5275 .ops = &r8a77990_pinmux_ops,
5276 .unlock_reg = 0xe6060000, /* PMMR */
5277
5278 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5279
5280 .pins = pinmux_pins,
5281 .nr_pins = ARRAY_SIZE(pinmux_pins),
5282 .groups = pinmux_groups.common,
5283 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
5284 .functions = pinmux_functions.common,
5285 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
5286
5287 .cfg_regs = pinmux_config_regs,
5288 .bias_regs = pinmux_bias_regs,
5289 .ioctrl_regs = pinmux_ioctrl_regs,
5290
5291 .pinmux_data = pinmux_data,
5292 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5293 };
5294 #endif
5295
5296 #ifdef CONFIG_PINCTRL_PFC_R8A77990
5297 const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5298 .name = "r8a77990_pfc",
5299 .ops = &r8a77990_pinmux_ops,
5300 .unlock_reg = 0xe6060000, /* PMMR */
5301
5302 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5303
5304 .pins = pinmux_pins,
5305 .nr_pins = ARRAY_SIZE(pinmux_pins),
5306 .groups = pinmux_groups.common,
5307 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
5308 ARRAY_SIZE(pinmux_groups.automotive),
5309 .functions = pinmux_functions.common,
5310 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
5311 ARRAY_SIZE(pinmux_functions.automotive),
5312
5313 .cfg_regs = pinmux_config_regs,
5314 .bias_regs = pinmux_bias_regs,
5315 .ioctrl_regs = pinmux_ioctrl_regs,
5316
5317 .pinmux_data = pinmux_data,
5318 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5319 };
5320 #endif
5321
