Searched refs:vdsc_cfg (Results 1 – 3 of 3) sorted by relevance
258 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) in drm_dsc_compute_rc_parameters() argument268 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { in drm_dsc_compute_rc_parameters()270 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, in drm_dsc_compute_rc_parameters()274 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()275 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters()279 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, in drm_dsc_compute_rc_parameters()283 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()284 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters()288 if (vdsc_cfg->convert_rgb) in drm_dsc_compute_rc_parameters()289 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + in drm_dsc_compute_rc_parameters()[all …]
325 struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; in intel_dp_compute_dsc_params() local332 vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; in intel_dp_compute_dsc_params()333 vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; in intel_dp_compute_dsc_params()334 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dp_compute_dsc_params()341 if (vdsc_cfg->pic_height % 8 == 0) in intel_dp_compute_dsc_params()342 vdsc_cfg->slice_height = 8; in intel_dp_compute_dsc_params()343 else if (vdsc_cfg->pic_height % 4 == 0) in intel_dp_compute_dsc_params()344 vdsc_cfg->slice_height = 4; in intel_dp_compute_dsc_params()346 vdsc_cfg->slice_height = 2; in intel_dp_compute_dsc_params()349 vdsc_cfg->dsc_version_major = in intel_dp_compute_dsc_params()[all …]
607 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
