| /Linux-v5.4/drivers/gpu/drm/amd/amdkfd/ |
| D | kfd_kernel_queue_v9.c | 94 packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8); in pm_map_process_v9()
96 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); in pm_map_process_v9()
99 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_v9()
104 upper_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
142 packet->ib_base_hi = upper_32_bits(ib); in pm_runlist_v9()
167 packet->gws_mask_hi = upper_32_bits(res->gws_mask); in pm_set_resources_v9()
170 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_v9()
231 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_v9()
237 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v9()
336 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_v9()
[all …]
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| D | kfd_kernel_queue_v10.c | 97 upper_32_bits(qpd->tba_addr >> 8); in pm_map_process_v10()
99 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); in pm_map_process_v10()
103 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_v10()
108 upper_32_bits(vm_page_table_base_addr); in pm_map_process_v10()
146 packet->ib_base_hi = upper_32_bits(ib); in pm_runlist_v10()
198 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_v10()
204 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v10()
293 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_v10()
295 packet->data_hi = upper_32_bits((uint64_t)fence_value); in pm_query_status_v10()
325 packet->address_hi = upper_32_bits(gpu_addr); in pm_release_mem_v10()
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| D | kfd_kernel_queue_vi.c | 110 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_vi()
149 packet->bitfields3.ib_base_hi = upper_32_bits(ib); in pm_runlist_vi()
174 packet->gws_mask_hi = upper_32_bits(res->gws_mask); in pm_set_resources_vi()
177 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_vi()
229 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
235 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
323 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_vi()
325 packet->data_hi = upper_32_bits((uint64_t)fence_value); in pm_query_status_vi()
353 packet->address_hi = upper_32_bits(gpu_addr); in pm_release_mem_vi()
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| D | kfd_mqd_manager_vi.c | 116 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
130 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8); in init_mqd()
132 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8); in init_mqd()
143 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
184 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
187 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in __update_mqd()
189 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in __update_mqd()
216 upper_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
361 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
363 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
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| D | kfd_mqd_manager_v10.c | 128 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
148 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
188 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
191 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
193 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
215 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
362 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
364 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
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| D | kfd_mqd_manager_v9.c | 147 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
169 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
206 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
209 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
211 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
235 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
380 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
382 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
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| D | kfd_mqd_manager_cik.c | 116 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
207 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
209 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in __update_mqd()
248 m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
250 m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
330 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
332 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_hiq()
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| /Linux-v5.4/drivers/gpu/drm/radeon/ |
| D | si_dma.c | 83 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pages()
84 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pages()
122 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_write_pages()
134 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pages()
174 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pages()
178 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_set_pages()
266 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma()
267 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()
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| D | evergreen_dma.c | 49 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
79 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in evergreen_dma_ring_ib_execute()
90 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
143 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in evergreen_copy_dma()
144 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in evergreen_copy_dma()
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| D | ni_dma.c | 135 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in cayman_dma_ring_ib_execute()
146 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
223 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume()
331 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_copy_pages()
332 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in cayman_dma_vm_copy_pages()
371 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_write_pages()
383 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_write_pages()
423 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_set_pages()
427 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_set_pages()
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| D | r600_dma.c | 144 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
256 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
296 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit()
323 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in r600_dma_semaphore_ring_emit()
361 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test()
416 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in r600_dma_ring_ib_execute()
427 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in r600_dma_ring_ib_execute()
479 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | in r600_copy_dma()
480 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
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| D | cik_sdma.c | 146 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_sdma_ring_ib_execute()
156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
209 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_fence_ring_emit()
238 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_semaphore_ring_emit()
401 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
615 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_dma()
617 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_dma()
671 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
729 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ib_test()
818 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pages()
[all …]
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| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | si_dma.c | 76 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
98 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
105 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
106 amdgpu_ring_write(ring, upper_32_bits(seq)); in si_dma_ring_emit_fence()
159 WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); in si_dma_start()
225 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in si_dma_ring_test_ring()
276 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib()
324 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pte()
325 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pte()
347 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in si_dma_vm_write_pte()
[all …]
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| D | sdma_v2_4.c | 264 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
315 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
323 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
324 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
456 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v2_4_gfx_resume()
571 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
624 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
678 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v2_4_vm_copy_pte()
680 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_copy_pte()
703 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_write_pte()
[all …]
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| D | sdma_v5_0.c | 238 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
334 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
337 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
348 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
352 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
392 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
395 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
448 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
459 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
460 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
[all …]
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| D | cik_sdma.c | 235 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
283 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence()
291 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence()
292 amdgpu_ring_write(ring, upper_32_bits(seq)); in cik_sdma_ring_emit_fence()
478 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
636 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
689 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
739 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pte()
741 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_copy_pte()
764 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_write_pte()
[all …]
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| D | sdma_v3_0.c | 438 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
489 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
497 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
498 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v3_0_ring_emit_fence()
695 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v3_0_gfx_resume()
721 upper_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume()
843 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v3_0_ring_test_ring()
896 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v3_0_ring_test_ib()
949 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v3_0_vm_copy_pte()
951 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v3_0_vm_copy_pte()
[all …]
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| /Linux-v5.4/drivers/net/ethernet/apm/xgene-v2/ |
| D | ring.c | 28 dma_h = upper_32_bits(next_dma); in xge_setup_desc()
40 xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr)); in xge_update_tx_desc_addr()
52 xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr)); in xge_update_rx_desc_addr()
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| /Linux-v5.4/drivers/pci/controller/ |
| D | pci-xgene.c | 302 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
306 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
392 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
394 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); in xgene_pcie_setup_ob_reg()
396 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
404 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
458 upper_32_bits(pim) | EN_COHERENCY); in xgene_pcie_setup_pims()
460 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); in xgene_pcie_setup_pims()
517 writel(upper_32_bits(cpu_addr), bar_addr + 0x4); in xgene_pcie_setup_ib_reg()
527 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr)); in xgene_pcie_setup_ib_reg()
[all …]
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| /Linux-v5.4/arch/x86/include/asm/ |
| D | mshyperv.h | 92 u32 input_address_hi = upper_32_bits(input_address); in hv_do_hypercall()
94 u32 output_address_hi = upper_32_bits(output_address); in hv_do_hypercall()
127 u32 input1_hi = upper_32_bits(input1); in hv_do_fast_hypercall8()
160 u32 input1_hi = upper_32_bits(input1); in hv_do_fast_hypercall16()
162 u32 input2_hi = upper_32_bits(input2); in hv_do_fast_hypercall16()
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| /Linux-v5.4/include/linux/ |
| D | goldfish.h | 18 writel(upper_32_bits(addr), porth); in gf_write_ptr()
28 writel(upper_32_bits(addr), porth); in gf_write_dma_addr()
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| /Linux-v5.4/drivers/media/pci/pt3/ |
| D | pt3_dma.c | 54 iowrite32(upper_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
185 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
191 d->addr_h = upper_32_bits(data_addr); in pt3_alloc_dmabuf()
196 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
205 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
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| /Linux-v5.4/drivers/firmware/xilinx/ |
| D | zynqmp.c | 91 ret_payload[1] = upper_32_bits(res.a0); in do_fw_call_smc()
93 ret_payload[3] = upper_32_bits(res.a1); in do_fw_call_smc()
121 ret_payload[1] = upper_32_bits(res.a0); in do_fw_call_hvc()
123 ret_payload[3] = upper_32_bits(res.a1); in do_fw_call_hvc()
400 upper_32_bits(rate), in zynqmp_pm_clock_setrate()
559 upper_32_bits(address), size, flags, NULL); in zynqmp_pm_fpga_load()
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| /Linux-v5.4/drivers/soc/fsl/qbman/ |
| D | dpaa_sys.c | 75 res_array[0] = cpu_to_be32(upper_32_bits(*addr)); in qbman_init_private_mem()
77 res_array[2] = cpu_to_be32(upper_32_bits(*size)); in qbman_init_private_mem()
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| /Linux-v5.4/drivers/gpu/drm/nouveau/ |
| D | nvc0_fence.c | 37 OUT_RING (chan, upper_32_bits(virtual)); in nvc0_fence_emit32()
53 OUT_RING (chan, upper_32_bits(virtual)); in nvc0_fence_sync32()
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