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Searched refs:tiling_flags (Results 1 – 25 of 27) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/radeon/
Dradeon_object.c594 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
599 lobj->tiling_flags = lobj->robj->tiling_flags; in radeon_bo_list_validate()
615 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
654 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
676 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
684 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
685 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
686 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags()
687 …tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; in radeon_bo_set_tiling_flags()
688 …stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCI… in radeon_bo_set_tiling_flags()
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Dradeon_fb.c134 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local
161 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
166 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object()
169 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object()
175 if (tiling_flags) { in radeonfb_create_pinned_object()
177 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
Dradeon_object.h147 u32 tiling_flags, u32 pitch);
149 u32 *tiling_flags, u32 *pitch);
Dr200.c221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
Dr300.c723 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
725 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
727 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
792 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
794 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
796 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
877 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
879 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
881 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
Dradeon_legacy_crtc.c386 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
466 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
483 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
Devergreen_cs.c93 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
95 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
97 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1181 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1182 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1185 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1366 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1367 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1384 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
[all …]
Datombios_crtc.c1155 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1193 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1276 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1277 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1350 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1477 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1513 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1589 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1591 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1594 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
[all …]
Dr100.c1283 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1285 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1625 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1627 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1706 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1708 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3094 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3101 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
3104 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3107 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
[all …]
Dr600_cs.c1044 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1143 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1146 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1474 u32 tiling_flags) in r600_check_texture_resource() argument
1496 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1498 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1985 reloc->tiling_flags); in r600_packet3_check()
Dradeon_gem.c512 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
533 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
Dradeon_vm.c146 list[0].tiling_flags = 0; in radeon_vm_get_bos()
158 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
Dradeon_display.c491 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local
537 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target()
545 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
Dradeon.h352 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
466 uint32_t tiling_flags; member
498 u32 tiling_flags; member
1935 uint32_t tiling_flags, uint32_t pitch,
Dradeon_asic.h91 uint32_t tiling_flags, uint32_t pitch,
339 uint32_t tiling_flags, uint32_t pitch,
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_fb.c129 u32 tiling_flags = 0, domain; in amdgpufb_create_pinned_object() local
158 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); in amdgpufb_create_pinned_object()
164 if (tiling_flags) { in amdgpufb_create_pinned_object()
166 tiling_flags); in amdgpufb_create_pinned_object()
Damdgpu_object.h89 u64 tiling_flags; member
257 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
258 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
Damdgpu_object.c1076 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument
1081 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1084 bo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags()
1096 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument
1100 if (tiling_flags) in amdgpu_bo_get_tiling_flags()
1101 *tiling_flags = bo->tiling_flags; in amdgpu_bo_get_tiling_flags()
Ddce_v8_0.c1768 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local
1806 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v8_0_crtc_do_set_base()
1809 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1891 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1894 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1895 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1896 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1897 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1898 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
1907 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
Ddce_v6_0.c1797 uint64_t fb_location, tiling_flags; in dce_v6_0_crtc_do_set_base() local
1834 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v6_0_crtc_do_set_base()
1917 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1920 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
1921 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1922 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1923 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1924 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
1932 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1936 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
Ddce_v10_0.c1839 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local
1877 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v10_0_crtc_do_set_base()
1880 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1970 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1973 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1974 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1975 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1976 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1977 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
1990 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c1881 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local
1919 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v11_0_crtc_do_set_base()
1922 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2012 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2015 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2016 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2017 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2018 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2019 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2032 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
Damdgpu_display.c161 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local
216 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target()
/Linux-v5.4/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c2660 uint64_t *tiling_flags) in get_fb_info() argument
2672 if (tiling_flags) in get_fb_info()
2673 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); in get_fb_info()
2680 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) in get_dcc_address() argument
2682 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); in get_dcc_address()
2753 const uint64_t tiling_flags, in fill_plane_buffer_attributes() argument
2809 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in fill_plane_buffer_attributes()
2812 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_plane_buffer_attributes()
2813 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_plane_buffer_attributes()
2814 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_plane_buffer_attributes()
[all …]
/Linux-v5.4/include/uapi/drm/
Dradeon_drm.h858 __u32 tiling_flags; member
864 __u32 tiling_flags; member

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