| /Linux-v5.4/drivers/gpu/drm/i915/gem/ |
| D | i915_gem_tiling.c | 54 u32 size, unsigned int tiling, unsigned int stride) in i915_gem_fence_size() argument
60 if (tiling == I915_TILING_NONE) in i915_gem_fence_size()
66 stride *= i915_gem_tile_height(tiling); in i915_gem_fence_size()
94 unsigned int tiling, unsigned int stride) in i915_gem_fence_alignment() argument
102 if (tiling == I915_TILING_NONE) in i915_gem_fence_alignment()
112 return i915_gem_fence_size(i915, size, tiling, stride); in i915_gem_fence_alignment()
118 unsigned int tiling, unsigned int stride) in i915_tiling_ok() argument
124 if (tiling == I915_TILING_NONE) in i915_tiling_ok()
127 if (tiling > I915_TILING_LAST) in i915_tiling_ok()
148 (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))) in i915_tiling_ok()
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| D | i915_gem_object.h | 192 i915_gem_tile_height(unsigned int tiling) in i915_gem_tile_height() argument
194 GEM_BUG_ON(!tiling); in i915_gem_tile_height()
195 return tiling == I915_TILING_Y ? 32 : 8; in i915_gem_tile_height()
212 unsigned int tiling, unsigned int stride);
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| /Linux-v5.4/drivers/gpu/drm/tegra/ |
| D | fb.c | 43 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling() argument
49 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; in tegra_fb_get_tiling()
50 tiling->value = 0; in tegra_fb_get_tiling()
54 tiling->mode = TEGRA_BO_TILING_MODE_TILED; in tegra_fb_get_tiling()
55 tiling->value = 0; in tegra_fb_get_tiling()
59 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
60 tiling->value = 0; in tegra_fb_get_tiling()
64 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
65 tiling->value = 1; in tegra_fb_get_tiling()
69 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
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| D | plane.h | 42 struct tegra_bo_tiling tiling; member
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| D | hub.c | 331 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_shared_plane_atomic_check() local
345 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_shared_plane_atomic_check()
349 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_shared_plane_atomic_check()
492 unsigned long height = state->tiling.value; in tegra_shared_plane_atomic_update()
495 switch (state->tiling.mode) { in tegra_shared_plane_atomic_update()
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| D | gem.h | 43 struct tegra_bo_tiling tiling; member
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| D | plane.c | 54 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
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| D | dc.c | 414 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
416 switch (window->tiling.mode) { in tegra_dc_setup_window()
433 switch (window->tiling.mode) { in tegra_dc_setup_window()
605 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local
632 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_plane_atomic_check()
636 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
713 window.tiling = state->tiling; in tegra_plane_atomic_update()
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| D | drm.h | 175 struct tegra_bo_tiling *tiling);
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| D | drm.c | 800 bo->tiling.mode = mode; in tegra_gem_set_tiling()
801 bo->tiling.value = value; in tegra_gem_set_tiling()
822 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
835 args->value = bo->tiling.value; in tegra_gem_get_tiling()
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| D | dc.h | 143 struct tegra_bo_tiling tiling; member
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| D | gem.c | 295 bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED; in tegra_bo_create()
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| /Linux-v5.4/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_mman.c | 20 unsigned int tiling; member
33 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
39 if (tile->tiling == I915_TILING_X) { in tiled_offset()
89 __func__, tile->tiling, tile->stride)) in check_partial_mapping()
92 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); in check_partial_mapping()
95 tile->tiling, tile->stride, err); in check_partial_mapping()
99 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); in check_partial_mapping()
158 tile->tiling ? tile_row_pages(obj) : 0, in check_partial_mapping()
159 vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride, in check_partial_mapping()
184 int tiling; in igt_partial_tiling() local
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| /Linux-v5.4/drivers/gpu/drm/vc4/ |
| D | vc4_render_cl.c | 440 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup() local
491 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_surface_setup()
525 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_surface_setup()
539 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup() local
568 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_render_config_surface_setup()
586 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_render_config_surface_setup()
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| D | vc4_plane.c | 598 u32 tiling, src_y; in vc4_plane_mode_set() local
636 tiling = SCALER_CTL0_TILING_LINEAR; in vc4_plane_mode_set()
699 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
732 tiling = SCALER_CTL0_TILING_64B; in vc4_plane_mode_set()
736 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
740 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
787 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
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| /Linux-v5.4/drivers/staging/media/ipu3/ |
| D | ipu3-css-params.c | 315 unsigned int tiling; member
428 unsigned int tiling = 0; in imgu_css_osys_calc_frame_and_stripe_params() local
468 &tiling); in imgu_css_osys_calc_frame_and_stripe_params()
474 frame_params[pin].tiling = tiling; in imgu_css_osys_calc_frame_and_stripe_params()
1003 fr_pr->tiling = frame_params[pin].tiling; in imgu_css_osys_calc()
1086 if (frame_params[pin].tiling) { in imgu_css_osys_calc()
1155 param->tiling = frame_params[pin].tiling; in imgu_css_osys_calc()
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| D | ipu3-abi.h | 919 u32 tiling; member
1025 u32 tiling; /* enum imgu_abi_osys_tiling */ member
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| /Linux-v5.4/drivers/gpu/drm/i915/ |
| D | i915_gem_fence_reg.c | 126 unsigned int tiling = i915_gem_object_get_tiling(vma->obj); in i915_write_fence_reg() local
127 bool is_y_tiled = tiling == I915_TILING_Y; in i915_write_fence_reg()
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20.c | 325 unsigned int tiling, in get_meta_and_pte_attr() argument
330 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
401 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
439 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
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| D | display_rq_dlg_calc_20v2.c | 325 unsigned int tiling, in get_meta_and_pte_attr() argument
330 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
401 (enum dm_swizzle_mode)(tiling), in get_meta_and_pte_attr()
439 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 313 unsigned int tiling, in get_meta_and_pte_attr() argument
319 bool surf_linear = (tiling == dm_sw_linear); in get_meta_and_pte_attr()
394 (enum dm_swizzle_mode) (tiling), in get_meta_and_pte_attr()
432 if (tiling != dm_sw_linear) in get_meta_and_pte_attr()
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 371 int tiling, in dml1_rq_dlg_get_row_heights() argument
376 bool surf_linear = (tiling == dm_sw_linear); in dml1_rq_dlg_get_row_heights()
427 if (tiling != dm_sw_linear) in dml1_rq_dlg_get_row_heights()
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| /Linux-v5.4/Documentation/gpu/ |
| D | i915.rst | 407 :doc: tiling swizzling details
416 :doc: buffer object tiling
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| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_display.c | 3078 switch (plane_config->tiling) { in intel_alloc_initial_plane_obj()
3083 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling; in intel_alloc_initial_plane_obj()
3086 MISSING_CASE(plane_config->tiling); in intel_alloc_initial_plane_obj()
3267 if (plane_config->tiling) in intel_find_initial_plane_obj()
8622 plane_config->tiling = I915_TILING_X; in i9xx_get_initial_plane_config()
8642 if (plane_config->tiling) in i9xx_get_initial_plane_config()
9800 u32 val, base, offset, stride_mult, tiling, alpha; in skylake_get_initial_plane_config() local
9839 tiling = val & PLANE_CTL_TILED_MASK; in skylake_get_initial_plane_config()
9840 switch (tiling) { in skylake_get_initial_plane_config()
9845 plane_config->tiling = I915_TILING_X; in skylake_get_initial_plane_config()
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| D | intel_display_types.h | 579 unsigned int tiling; member
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