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Searched refs:tg_inst (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_hwseq.c168 unsigned int tg_inst) in dce_crtc_switch_to_clk_src() argument
171 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
177 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
181 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
187 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
191 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src()
192 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
196 clk_src->id, tg_inst); in dce_crtc_switch_to_clk_src()
Ddce_stream_encoder.c1589 int tg_inst, bool enable) in setup_stereo_sync() argument
1592 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync()
1598 int tg_inst) in dig_connect_to_otg() argument
1602 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in dig_connect_to_otg()
1608 uint32_t tg_inst = 0; in dig_source_otg() local
1611 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg()
1613 return tg_inst; in dig_source_otg()
Ddce_hwseq.h837 unsigned int tg_inst);
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/hw/
Dstream_encoder.h201 int tg_inst,
209 int tg_inst);
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c1529 int tg_inst, bool enable) in enc1_setup_stereo_sync() argument
1532 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in enc1_setup_stereo_sync()
1538 int tg_inst) in enc1_dig_connect_to_otg() argument
1542 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in enc1_dig_connect_to_otg()
1548 uint32_t tg_inst = 0; in enc1_dig_source_otg() local
1551 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in enc1_dig_source_otg()
1553 return tg_inst; in enc1_dig_source_otg()
Ddcn10_stream_encoder.h567 int tg_inst, bool enable);
599 int tg_inst);
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c1857 unsigned int inst, tg_inst; in acquire_resource_from_hw_enabled_state() local
1878 tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]); in acquire_resource_from_hw_enabled_state()
1880 if (tg_inst >= pool->timing_generator_count) in acquire_resource_from_hw_enabled_state()
1883 if (!res_ctx->pipe_ctx[tg_inst].stream) { in acquire_resource_from_hw_enabled_state()
1884 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; in acquire_resource_from_hw_enabled_state()
1886 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; in acquire_resource_from_hw_enabled_state()
1887 pipe_ctx->plane_res.mi = pool->mis[tg_inst]; in acquire_resource_from_hw_enabled_state()
1888 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; in acquire_resource_from_hw_enabled_state()
1889 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; in acquire_resource_from_hw_enabled_state()
1890 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; in acquire_resource_from_hw_enabled_state()
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Ddc.c974 unsigned int enc_inst, tg_inst; in dc_validate_seamless_boot_timing() local
995 tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg( in dc_validate_seamless_boot_timing()
998 if (tg_inst >= dc->res_pool->timing_generator_count) in dc_validate_seamless_boot_timing()
1001 tg = dc->res_pool->timing_generators[tg_inst]; in dc_validate_seamless_boot_timing()
1014 tg_inst, &pix_clk_100hz); in dc_validate_seamless_boot_timing()