Searched refs:tc_cfg (Results 1 – 8 of 8) sorted by relevance
156 struct qlcnic_dcb_tc_cfg tc_cfg[QLC_DCB_MAX_TC]; member660 struct qlcnic_dcb_tc_cfg *tc_cfg; in qlcnic_dcb_fill_cee_tc_params() local665 tc_cfg = &type->tc_cfg[tc]; in qlcnic_dcb_fill_cee_tc_params()666 tc_cfg->valid = true; in qlcnic_dcb_fill_cee_tc_params()667 tc_cfg->up_tc_map |= QLC_DCB_GET_MAP(i); in qlcnic_dcb_fill_cee_tc_params()671 tc_cfg->prio_cfg[i].valid = true; in qlcnic_dcb_fill_cee_tc_params()672 tc_cfg->prio_cfg[i].pfc_type = QLC_PFC_FULL; in qlcnic_dcb_fill_cee_tc_params()680 tc_cfg->pgid = pgid; in qlcnic_dcb_fill_cee_tc_params()682 tc_cfg->prio_type = QLC_PRIO_LINK; in qlcnic_dcb_fill_cee_tc_params()683 type->pg_cfg[tc_cfg->pgid].prio_count++; in qlcnic_dcb_fill_cee_tc_params()[all …]
354 struct dpu_hw_tear_check tc_cfg = { 0 }; in dpu_encoder_phys_cmd_tearcheck_config() local398 tc_cfg.vsync_count = vsync_hz / in dpu_encoder_phys_cmd_tearcheck_config()402 tc_cfg.hw_vsync_mode = 0; in dpu_encoder_phys_cmd_tearcheck_config()409 tc_cfg.sync_cfg_height = 0xFFF0; in dpu_encoder_phys_cmd_tearcheck_config()410 tc_cfg.vsync_init_val = mode->vdisplay; in dpu_encoder_phys_cmd_tearcheck_config()411 tc_cfg.sync_threshold_start = DEFAULT_TEARCHECK_SYNC_THRESH_START; in dpu_encoder_phys_cmd_tearcheck_config()412 tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE; in dpu_encoder_phys_cmd_tearcheck_config()413 tc_cfg.start_pos = mode->vdisplay; in dpu_encoder_phys_cmd_tearcheck_config()414 tc_cfg.rd_ptr_irq = mode->vdisplay + 1; in dpu_encoder_phys_cmd_tearcheck_config()422 phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos, in dpu_encoder_phys_cmd_tearcheck_config()[all …]
27 if (netdev_set_num_tc(netdev, vsi->tc_cfg.numtc)) in ice_vsi_cfg_netdev_tc()33 if (vsi->tc_cfg.ena_tc & BIT(i)) in ice_vsi_cfg_netdev_tc()35 vsi->tc_cfg.tc_info[i].netdev_tc, in ice_vsi_cfg_netdev_tc()36 vsi->tc_cfg.tc_info[i].qcount_tx, in ice_vsi_cfg_netdev_tc()37 vsi->tc_cfg.tc_info[i].qoffset); in ice_vsi_cfg_netdev_tc()43 netdev_tc = vsi->tc_cfg.tc_info[ets_tc].netdev_tc; in ice_vsi_cfg_netdev_tc()126 if (!(vsi->tc_cfg.ena_tc & BIT(n))) in ice_vsi_cfg_dcb_rings()129 qoffset = vsi->tc_cfg.tc_info[n].qoffset; in ice_vsi_cfg_dcb_rings()130 qcount = vsi->tc_cfg.tc_info[n].qcount_tx; in ice_vsi_cfg_dcb_rings()
880 if (vsi->tc_cfg.numtc) { in ice_vsi_setup_q_map()881 if (!(vsi->tc_cfg.ena_tc & BIT(0))) in ice_vsi_setup_q_map()888 vsi->tc_cfg.numtc++; in ice_vsi_setup_q_map()889 vsi->tc_cfg.ena_tc |= 1; in ice_vsi_setup_q_map()892 rx_numq_tc = qcount_rx / vsi->tc_cfg.numtc; in ice_vsi_setup_q_map()895 tx_numq_tc = qcount_tx / vsi->tc_cfg.numtc; in ice_vsi_setup_q_map()929 if (!(vsi->tc_cfg.ena_tc & BIT(i))) { in ice_vsi_setup_q_map()931 vsi->tc_cfg.tc_info[i].qoffset = 0; in ice_vsi_setup_q_map()932 vsi->tc_cfg.tc_info[i].qcount_rx = 1; in ice_vsi_setup_q_map()933 vsi->tc_cfg.tc_info[i].qcount_tx = 1; in ice_vsi_setup_q_map()[all …]
276 struct ice_tc_cfg tc_cfg; member
2311 vsi->tc_cfg.tc_info[0].qcount_tx = num_txq; in ice_vc_cfg_qs_msg()2312 vsi->tc_cfg.tc_info[0].qcount_rx = num_rxq; in ice_vc_cfg_qs_msg()
2055 ice_vsi_cfg_netdev_tc(vsi, vsi->tc_cfg.ena_tc); in ice_cfg_netdev()
1271 u32 tc_cfg; in hns_dsaf_inode_init() local1275 tc_cfg = HNS_DSAF_I4TC_CFG; in hns_dsaf_inode_init()1277 tc_cfg = HNS_DSAF_I8TC_CFG; in hns_dsaf_inode_init()1312 dsaf_write_dev(dsaf_dev, reg, tc_cfg); in hns_dsaf_inode_init()
