Searched refs:target_itr (Results 1 – 12 of 12) sorted by relevance
1209 itr = rc->target_itr; in ice_update_itr()1241 (q_vector->tx.target_itr & ICE_ITR_ADAPTIVE_LATENCY)) { in ice_update_itr()1251 if (rc->target_itr == ICE_ITR_ADAPTIVE_MAX_USECS && in ice_update_itr()1252 (q_vector->rx.target_itr & ICE_ITR_MASK) == in ice_update_itr()1259 rc->target_itr &= ~ICE_ITR_ADAPTIVE_LATENCY; in ice_update_itr()1271 itr = rc->target_itr + ICE_ITR_ADAPTIVE_MIN_INC; in ice_update_itr()1319 rc->target_itr = itr; in ice_update_itr()1377 rx->target_itr = rx->itr_setting; in ice_update_ena_itr()1398 if (rx->target_itr < rx->current_itr) { in ice_update_ena_itr()1400 itr_val = ice_buildreg_itr(rx->itr_idx, rx->target_itr); in ice_update_ena_itr()[all …]
220 u16 target_itr; /* value in usecs divided by the hw->itr_gran */ member
1893 rc->target_itr = ITR_TO_REG(rc->itr_setting); in ice_cfg_itr()1895 rc->current_itr = rc->target_itr; in ice_cfg_itr()1907 rc->target_itr = ITR_TO_REG(rc->itr_setting); in ice_cfg_itr()1909 rc->current_itr = rc->target_itr; in ice_cfg_itr()
3307 rc->target_itr = in ice_set_rc_coalesce()
449 itr = rc->target_itr; in iavf_update_itr()463 (q_vector->tx.target_itr & IAVF_ITR_ADAPTIVE_LATENCY)) { in iavf_update_itr()473 if (rc->target_itr == IAVF_ITR_ADAPTIVE_MAX_USECS && in iavf_update_itr()474 (q_vector->rx.target_itr & IAVF_ITR_MASK) == in iavf_update_itr()481 rc->target_itr &= ~IAVF_ITR_ADAPTIVE_LATENCY; in iavf_update_itr()493 itr = rc->target_itr + IAVF_ITR_ADAPTIVE_MIN_INC; in iavf_update_itr()599 rc->target_itr = itr; in iavf_update_itr()1661 if (q_vector->rx.target_itr < q_vector->rx.current_itr) { in iavf_update_enable_itr()1664 q_vector->rx.target_itr); in iavf_update_enable_itr()1665 q_vector->rx.current_itr = q_vector->rx.target_itr; in iavf_update_enable_itr()[all …]
731 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting); in iavf_set_itr_per_queue()734 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting); in iavf_set_itr_per_queue()
420 u16 target_itr; /* target ITR setting for ring(s) */ member
314 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting); in iavf_map_vector_to_rxq()318 q_vector->rx.current_itr = q_vector->rx.target_itr; in iavf_map_vector_to_rxq()340 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting); in iavf_map_vector_to_txq()343 q_vector->tx.target_itr >> 1); in iavf_map_vector_to_txq()344 q_vector->tx.current_itr = q_vector->tx.target_itr; in iavf_map_vector_to_txq()
1039 itr = rc->target_itr; in i40e_update_itr()1053 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) { in i40e_update_itr()1063 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS && in i40e_update_itr()1064 (q_vector->rx.target_itr & I40E_ITR_MASK) == in i40e_update_itr()1071 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY; in i40e_update_itr()1083 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC; in i40e_update_itr()1189 rc->target_itr = itr; in i40e_update_itr()2526 if (q_vector->rx.target_itr < q_vector->rx.current_itr) { in i40e_update_enable_itr()2529 q_vector->rx.target_itr); in i40e_update_enable_itr()2530 q_vector->rx.current_itr = q_vector->rx.target_itr; in i40e_update_enable_itr()[all …]
463 u16 target_itr; /* target ITR setting for ring(s) */ member
3534 q_vector->rx.target_itr = in i40e_vsi_configure_msix()3537 q_vector->rx.target_itr); in i40e_vsi_configure_msix()3538 q_vector->rx.current_itr = q_vector->rx.target_itr; in i40e_vsi_configure_msix()3541 q_vector->tx.target_itr = in i40e_vsi_configure_msix()3544 q_vector->tx.target_itr); in i40e_vsi_configure_msix()3545 q_vector->tx.current_itr = q_vector->tx.target_itr; in i40e_vsi_configure_msix()3648 q_vector->rx.target_itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting); in i40e_configure_msi_and_legacy()3649 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr); in i40e_configure_msi_and_legacy()3650 q_vector->rx.current_itr = q_vector->rx.target_itr; in i40e_configure_msi_and_legacy()3652 q_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting); in i40e_configure_msi_and_legacy()[all …]
2836 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting); in i40e_set_itr_per_queue()2839 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting); in i40e_set_itr_per_queue()
