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Searched refs:speed_cntl (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/radeon/
Drv770.c2027 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2066 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
2067 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in rv770_pcie_gen2_enable()
2068 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in rv770_pcie_gen2_enable()
2079 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
2080 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in rv770_pcie_gen2_enable()
2081 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in rv770_pcie_gen2_enable()
2083 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
2084 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; in rv770_pcie_gen2_enable()
2085 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in rv770_pcie_gen2_enable()
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Dr600.c4493 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
4517 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4518 if (speed_cntl & LC_CURRENT_DATA_RATE) { in r600_pcie_gen2_enable()
4546 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4547 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in r600_pcie_gen2_enable()
4548 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in r600_pcie_gen2_enable()
4562 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; in r600_pcie_gen2_enable()
4563 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); in r600_pcie_gen2_enable()
4564 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; in r600_pcie_gen2_enable()
4565 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
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Devergreen.c5327 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
5346 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
5347 if (speed_cntl & LC_CURRENT_DATA_RATE) { in evergreen_pcie_gen2_enable()
5354 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || in evergreen_pcie_gen2_enable()
5355 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in evergreen_pcie_gen2_enable()
5361 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
5362 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in evergreen_pcie_gen2_enable()
5363 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in evergreen_pcie_gen2_enable()
5365 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
5366 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; in evergreen_pcie_gen2_enable()
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Dsi.c7091 u32 speed_cntl, current_data_rate; in si_pcie_gen3_enable() local
7115 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
7116 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> in si_pcie_gen3_enable()
7222 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; in si_pcie_gen3_enable()
7223 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; in si_pcie_gen3_enable()
7224 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in si_pcie_gen3_enable()
7236 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
7237 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; in si_pcie_gen3_enable()
7238 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in si_pcie_gen3_enable()
7241 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
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Dcik.c9508 u32 speed_cntl, current_data_rate; in cik_pcie_gen3_enable() local
9532 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
9533 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> in cik_pcie_gen3_enable()
9639 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; in cik_pcie_gen3_enable()
9640 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; in cik_pcie_gen3_enable()
9641 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
9653 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
9654 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; in cik_pcie_gen3_enable()
9655 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
9658 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
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Dsi_dpm.c5736 u32 speed_cntl; in si_get_current_pcie_speed() local
5738 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; in si_get_current_pcie_speed()
5739 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; in si_get_current_pcie_speed()
5741 return (u16)speed_cntl; in si_get_current_pcie_speed()
Dci_dpm.c4815 u32 speed_cntl = 0; in ci_get_current_pcie_speed() local
4817 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; in ci_get_current_pcie_speed()
4818 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; in ci_get_current_pcie_speed()
4820 return (u16)speed_cntl; in ci_get_current_pcie_speed()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dcik.c1388 u32 speed_cntl, current_data_rate; in cik_pcie_gen3_enable() local
1405 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1406 current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >> in cik_pcie_gen3_enable()
1518 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | in cik_pcie_gen3_enable()
1520 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; in cik_pcie_gen3_enable()
1521 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1533 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1534 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; in cik_pcie_gen3_enable()
1535 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1538 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
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Dsi.c1637 u32 speed_cntl, current_data_rate; in si_pcie_gen3_enable() local
1654 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
1655 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> in si_pcie_gen3_enable()
1756 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; in si_pcie_gen3_enable()
1757 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; in si_pcie_gen3_enable()
1758 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in si_pcie_gen3_enable()
1770 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
1771 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; in si_pcie_gen3_enable()
1772 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in si_pcie_gen3_enable()
1775 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
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Dsi_dpm.c6188 u32 speed_cntl; in si_get_current_pcie_speed() local
6190 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; in si_get_current_pcie_speed()
6191 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; in si_get_current_pcie_speed()
6193 return (u16)speed_cntl; in si_get_current_pcie_speed()