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Searched refs:sh_num (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dnv.c185 u32 sh_num, u32 reg_offset) in nv_read_indexed_register() argument
190 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
191 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
195 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
203 u32 sh_num, u32 reg_offset) in nv_get_register_value() argument
206 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
215 u32 sh_num, u32 reg_offset, u32 *value) in nv_read_register() argument
229 se_num, sh_num, reg_offset); in nv_read_register()
Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
Dcik.c1029 u32 sh_num, u32 reg_offset) in cik_get_register_value() argument
1034 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in cik_get_register_value()
1048 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1049 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in cik_get_register_value()
1053 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1124 u32 sh_num, u32 reg_offset, u32 *value) in cik_read_register() argument
1135 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
Dsoc15.c346 u32 sh_num, u32 reg_offset) in soc15_read_indexed_register() argument
351 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
352 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
356 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
364 u32 sh_num, u32 reg_offset) in soc15_get_register_value() argument
367 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
378 u32 sh_num, u32 reg_offset, u32 *value) in soc15_read_register() argument
392 se_num, sh_num, reg_offset); in soc15_read_register()
Dsi.c1019 u32 sh_num, u32 reg_offset) in si_get_register_value() argument
1024 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in si_get_register_value()
1036 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1037 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in si_get_register_value()
1041 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1093 u32 sh_num, u32 reg_offset, u32 *value) in si_read_register() argument
1104 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
Dvi.c553 u32 sh_num, u32 reg_offset) in vi_get_register_value() argument
558 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in vi_get_register_value()
572 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
573 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
577 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
648 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register() argument
659 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
Damdgpu_kms.c633 unsigned sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
641 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) in amdgpu_info_ioctl()
642 sh_num = 0xffffffff; in amdgpu_info_ioctl()
654 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
Damdgpu_gfx.h189 u32 sh_num, u32 instance);
Dgfx_v6_0.c1302 u32 sh_num, u32 instance) in gfx_v6_0_select_se_sh() argument
1311 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1316 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1317 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1321 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v6_0_select_se_sh()
Dgfx_v7_0.c1589 u32 se_num, u32 sh_num, u32 instance) in gfx_v7_0_select_se_sh() argument
1598 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1603 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1604 else if (sh_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1608 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v7_0_select_se_sh()
Damdgpu.h553 u32 sh_num, u32 reg_offset, u32 *value);
Dgfx_v10_0.c246 u32 sh_num, u32 instance);
1496 u32 sh_num, u32 instance) in gfx_v10_0_select_se_sh() argument
1513 if (sh_num == 0xffffffff) in gfx_v10_0_select_se_sh()
1517 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v10_0_select_se_sh()
Dgfx_v9_0.c732 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
2383 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) in gfx_v9_0_select_se_sh() argument
2397 if (sh_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2400 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
Dgfx_v8_0.c3449 u32 se_num, u32 sh_num, u32 instance) in gfx_v8_0_select_se_sh() argument
3463 if (sh_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3466 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dsi.c2952 u32 se_num, u32 sh_num) in si_select_se_sh() argument
2956 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2959 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); in si_select_se_sh()
2960 else if (sh_num == 0xffffffff) in si_select_se_sh()
2963 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in si_select_se_sh()
Dcik.c3040 u32 se_num, u32 sh_num) in cik_select_se_sh() argument
3044 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in cik_select_se_sh()
3047 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); in cik_select_se_sh()
3048 else if (sh_num == 0xffffffff) in cik_select_se_sh()
3051 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in cik_select_se_sh()