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Searched refs:set_rate (Results 1 – 25 of 244) sorted by relevance

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/Linux-v5.4/arch/arm/mach-omap1/
Dclock_data.c113 .set_rate = &omap1_set_sossi_rate,
123 .set_rate = omap1_clk_set_rate_ckctl_arm,
137 .set_rate = omap1_clk_set_rate_ckctl_arm,
217 .set_rate = omap1_clk_set_rate_ckctl_arm,
227 .set_rate = omap1_clk_set_rate_ckctl_arm,
239 .set_rate = &omap1_clk_set_rate_dsp_domain,
269 .set_rate = omap1_clk_set_rate_ckctl_arm,
390 .set_rate = omap1_clk_set_rate_ckctl_arm,
404 .set_rate = omap1_clk_set_rate_ckctl_arm,
424 .set_rate = &omap1_set_uart_rate,
[all …]
/Linux-v5.4/arch/arm/mach-ep93xx/
Dclock.c36 int (*set_rate)(struct clk *clk, unsigned long rate); member
96 .set_rate = set_keytchclk_rate,
103 .set_rate = set_keytchclk_rate,
118 .set_rate = set_div_rate,
125 .set_rate = set_div_rate,
133 .set_rate = set_i2s_sclk_rate,
141 .set_rate = set_i2s_lrclk_rate,
476 if (clk->set_rate) in clk_set_rate()
477 return clk->set_rate(clk, rate); in clk_set_rate()
/Linux-v5.4/drivers/clk/
Dclk-composite.c139 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate()
159 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
163 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
257 if (rate_ops->set_rate) { in clk_hw_register_composite()
259 clk_composite_ops->set_rate = in clk_hw_register_composite()
271 if (mux_ops->set_parent && rate_ops->set_rate) in clk_hw_register_composite()
/Linux-v5.4/drivers/clk/ti/
Ddpll.c37 .set_rate = &omap3_noncore_dpll_set_rate,
62 .set_rate = &omap3_noncore_dpll_set_rate,
75 .set_rate = &omap3_noncore_dpll_set_rate,
94 .set_rate = &omap2_reprogram_dpllcore,
116 .set_rate = &omap3_noncore_dpll_set_rate,
128 .set_rate = &omap3_dpll5_set_rate,
140 .set_rate = &omap3_dpll4_set_rate,
/Linux-v5.4/drivers/clk/actions/
Dowl-composite.c157 .set_rate = owl_comp_div_set_rate,
174 .set_rate = owl_comp_fact_set_rate,
186 .set_rate = owl_comp_fix_fact_set_rate,
/Linux-v5.4/drivers/clk/st/
Dclk-flexgen.c177 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
178 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); in flexgen_set_rate()
180 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
181 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); in flexgen_set_rate()
195 .set_rate = flexgen_set_rate,
/Linux-v5.4/drivers/sh/clk/
Dcpg.c197 .set_rate = sh_clk_div_set_rate,
203 .set_rate = sh_clk_div_set_rate,
330 .set_rate = sh_clk_div_set_rate,
382 .set_rate = sh_clk_div_set_rate,
462 .set_rate = fsidiv_set_rate,
Dcore.c490 if (likely(clk->ops && clk->ops->set_rate)) { in clk_set_rate()
491 ret = clk->ops->set_rate(clk, rate); in clk_set_rate()
583 if (likely(clkp->ops->set_rate)) in clks_core_resume()
584 clkp->ops->set_rate(clkp, rate); in clks_core_resume()
/Linux-v5.4/drivers/clk/mvebu/
Dclk-corediv.c203 .set_rate = clk_corediv_set_rate,
219 .set_rate = clk_corediv_set_rate,
232 .set_rate = clk_corediv_set_rate,
244 .set_rate = clk_corediv_set_rate,
/Linux-v5.4/drivers/clk/mxs/
Dclk-div.c57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
67 .set_rate = clk_div_set_rate,
/Linux-v5.4/arch/mips/loongson64/lemote-2f/
Dclock.c102 if (likely(clk->ops && clk->ops->set_rate)) { in clk_set_rate()
106 ret = clk->ops->set_rate(clk, rate, 0); in clk_set_rate()
/Linux-v5.4/arch/sh/kernel/cpu/sh4/
Dclock-sh4-202.c81 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
133 .set_rate = shoc_clk_set_rate,
/Linux-v5.4/drivers/clk/tegra/
Dclk-periph.c68 return div_ops->set_rate(div_hw, rate, parent_rate); in clk_periph_set_rate()
107 .set_rate = clk_periph_set_rate,
126 .set_rate = clk_periph_set_rate,
/Linux-v5.4/drivers/clk/ux500/
Dclk-prcmu.c197 .set_rate = clk_prcmu_set_rate,
214 .set_rate = clk_prcmu_set_rate,
241 .set_rate = clk_prcmu_set_rate,
/Linux-v5.4/drivers/clk/samsung/
Dclk-pll.c256 .set_rate = samsung_pll35xx_set_rate,
372 .set_rate = samsung_pll36xx_set_rate,
511 .set_rate = samsung_pll45xx_set_rate,
670 .set_rate = samsung_pll46xx_set_rate,
899 .set_rate = samsung_s3c2410_pll_set_rate,
907 .set_rate = samsung_s3c2410_pll_set_rate,
915 .set_rate = samsung_s3c2410_pll_set_rate,
1051 .set_rate = samsung_pll2550xx_set_rate,
1147 .set_rate = samsung_pll2650x_set_rate,
1241 .set_rate = samsung_pll2650xx_set_rate,
/Linux-v5.4/drivers/clk/imx/
Dclk-pllv3.c158 .set_rate = clk_pllv3_set_rate,
213 .set_rate = clk_pllv3_sys_set_rate,
302 .set_rate = clk_pllv3_av_set_rate,
395 .set_rate = clk_pllv3_vf610_set_rate,
Dclk-busy.c62 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
72 .set_rate = clk_busy_divider_set_rate,
/Linux-v5.4/include/linux/qed/
Dqed_iov_if.h54 int (*set_rate) (struct qed_dev *cdev, int vfid, member
/Linux-v5.4/sound/usb/6fire/
Dcontrol.h31 int (*set_rate)(struct control_runtime *rt, int rate); member
/Linux-v5.4/arch/mips/include/asm/
Dclock.h17 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id); member
/Linux-v5.4/drivers/staging/clocking-wizard/
DTODO4 - support for set_rate() operations (may benefit from Stephen Boyd's
/Linux-v5.4/drivers/clk/qcom/
Dclk-rcg2.c360 .set_rate = clk_rcg2_set_rate,
371 .set_rate = clk_rcg2_set_floor_rate,
497 .set_rate = clk_edp_pixel_set_rate,
555 .set_rate = clk_byte_set_rate,
625 .set_rate = clk_byte2_set_rate,
715 .set_rate = clk_pixel_set_rate,
802 .set_rate = clk_gfx3d_set_rate,
941 .set_rate = clk_rcg2_shared_set_rate,
Dclk-rcg.c815 .set_rate = clk_rcg_set_rate,
826 .set_rate = clk_rcg_bypass_set_rate,
837 .set_rate = clk_rcg_bypass2_set_rate,
849 .set_rate = clk_rcg_pixel_set_rate,
861 .set_rate = clk_rcg_esc_set_rate,
873 .set_rate = clk_rcg_lcc_set_rate,
885 .set_rate = clk_dyn_rcg_set_rate,
/Linux-v5.4/drivers/clk/at91/
Dclk-usb.c152 .set_rate = at91sam9x5_clk_usb_set_rate,
188 .set_rate = at91sam9x5_clk_usb_set_rate,
356 .set_rate = at91rm9200_clk_usb_set_rate,
/Linux-v5.4/sound/soc/codecs/
Dtlv320aic32x4-clk.c263 .set_rate = clk_aic32x4_pll_set_rate,
349 .set_rate = clk_aic32x4_div_set_rate,
377 .set_rate = clk_aic32x4_div_set_rate,

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