| /Linux-v5.4/drivers/mmc/host/ |
| D | sdhci.c | 59 sdhci_readw(host, SDHCI_HOST_VERSION)); in sdhci_dumpregs()
61 sdhci_readw(host, SDHCI_BLOCK_SIZE), in sdhci_dumpregs()
62 sdhci_readw(host, SDHCI_BLOCK_COUNT)); in sdhci_dumpregs()
65 sdhci_readw(host, SDHCI_TRANSFER_MODE)); in sdhci_dumpregs()
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); in sdhci_dumpregs()
82 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS), in sdhci_dumpregs()
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); in sdhci_dumpregs()
88 sdhci_readw(host, SDHCI_COMMAND), in sdhci_dumpregs()
97 sdhci_readw(host, SDHCI_HOST_CONTROL2)); in sdhci_dumpregs()
126 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
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| D | sdhci-pci-gli.c | 165 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
185 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
231 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_execute_tuning_9750()
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| D | sdhci-sprd.c | 162 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_sprd_sd_clk_off()
172 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_sprd_sd_clk_on()
312 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_set_uhs_signaling()
480 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_hs400_enhanced_strobe()
605 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); in sdhci_sprd_probe()
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| D | sdhci_f_sdh30.c | 91 if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0) in sdhci_f_sdh30_reset()
182 ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG); in sdhci_f_sdh30_probe()
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| D | sdhci-pci-o2micro.c | 119 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
146 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) in sdhci_o2_get_cd()
190 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); in sdhci_o2_set_tuning_mode()
202 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_o2_execute_tuning()
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| D | sdhci-cns3xxx.c | 62 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) in sdhci_cns3xxx_set_clock()
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| D | sdhci-pci-dwc-mshc.c | 36 vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R); in sdhci_snps_set_clock()
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| D | sdhci-pci-arasan.c | 101 val = sdhci_readw(host, PHY_ADDR_REG); in arasan_phy_addr_poll()
125 *data = sdhci_readw(host, PHY_DAT_REG) & DATA_MASK; in arasan_phy_read()
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| D | sdhci-xenon.c | 37 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
195 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_uhs_signaling()
281 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_ios()
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| D | sdhci-of-at91.c | 64 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_at91_set_clock()
78 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) in sdhci_at91_set_clock()
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| D | sdhci-sirf.c | 84 clock_setting = sdhci_readw(host, SDHCI_CLK_DELAY_SETTING); in sdhci_sirf_execute_tuning()
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| D | sdhci.h | 683 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() function
721 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw() function
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| D | sdhci-s3c.c | 383 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in sdhci_cmu_set_clock()
399 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) in sdhci_cmu_set_clock()
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| D | sdhci-of-esdhc.c | 900 command = SDHCI_GET_CMD(sdhci_readw(host, in esdhc_irq()
903 sdhci_readw(host, SDHCI_BLOCK_COUNT) && in esdhc_irq()
1029 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); in esdhc_init()
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| D | sdhci-st.c | 261 u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_st_set_uhs_signaling()
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| D | sdhci-pxav3.c | 250 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in pxav3_set_uhs_signaling()
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| D | sdhci-xenon-phy.c | 360 if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) & in xenon_emmc_phy_enable_dll()
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| D | sdhci-pci-core.c | 1477 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1481 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
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| D | sdhci-msm.c | 1208 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_set_uhs_signaling()
1541 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in __sdhci_msm_set_clock()
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| D | sdhci-tegra.c | 223 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in tegra_sdhci_configure_card_clk()
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| D | sdhci-esdhc-imx.c | 1275 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); in esdhc_cqe_enable()
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