Home
last modified time | relevance | path

Searched refs:sdhci_readl (Results 1 – 18 of 18) sorted by relevance

/Linux-v5.4/drivers/mmc/host/
Dsdhci-xenon-phy.c235 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
265 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
331 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
336 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
392 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); in xenon_emmc_phy_config_tuning()
402 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); in xenon_emmc_phy_config_tuning()
420 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe()
426 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); in xenon_emmc_phy_disable_strobe()
430 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); in xenon_emmc_phy_disable_strobe()
454 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj()
[all …]
Dsdhci-pci-gli.c71 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_on()
88 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_off()
112 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); in gli_set_9750()
113 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
114 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); in gli_set_9750()
115 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750()
116 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); in gli_set_9750()
117 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
198 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750_rx_inv()
Dsdhci-of-esdhc.c497 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); in esdhc_of_enable_dma()
537 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_clock_enable()
552 if (sdhci_readl(host, ESDHC_PRSSTAT) & val) in esdhc_clock_enable()
594 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_of_set_clock()
632 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_of_set_clock()
640 temp = sdhci_readl(host, ESDHC_TBCTL); in esdhc_of_set_clock()
642 temp = sdhci_readl(host, ESDHC_SDCLKCTL); in esdhc_of_set_clock()
646 temp = sdhci_readl(host, ESDHC_DLLCFG0); in esdhc_of_set_clock()
651 temp = sdhci_readl(host, ESDHC_TBCTL); in esdhc_of_set_clock()
655 temp = sdhci_readl(host, ESDHC_DMA_SYSCTL); in esdhc_of_set_clock()
[all …]
Dsdhci-xenon.c29 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
57 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle()
73 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_acg()
87 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_enable_sdhc()
105 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_disable_sdhc()
116 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran()
126 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
138 reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL); in xenon_retune_setup()
143 reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup()
146 reg = sdhci_readl(host, SDHCI_INT_ENABLE); in xenon_retune_setup()
[all …]
Dsdhci-bcm-kona.c67 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
71 while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) { in sdhci_bcm_kona_sd_reset()
79 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
99 val = sdhci_readl(host, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init()
104 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init()
138 val = sdhci_readl(host, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
Dsdhci_f_sdh30.c59 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
71 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch()
76 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch()
97 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset()
188 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
193 reg = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_f_sdh30_probe()
Dsdhci-pci-dwc-mshc.c39 reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock()
47 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
63 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
Dsdhci-pci-o2micro.c81 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_o2_wait_card_detect_stable()
103 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
137 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
149 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in sdhci_o2_get_cd()
168 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_pll_dll_wdt_control()
248 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
524 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_pci_o2_probe_slot()
539 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); in sdhci_pci_o2_probe_slot()
569 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
Dsdhci-sprd.c108 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config()
182 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); in sdhci_sprd_set_dll_invert()
227 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
240 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
246 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
253 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
623 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_sprd_probe()
624 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in sdhci_sprd_probe()
Dsdhci-tegra.c323 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap()
342 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); in tegra_sdhci_hs400_enhanced_strobe()
367 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); in tegra_sdhci_reset()
368 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_reset()
399 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_reset()
418 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad()
436 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset()
481 reg = sdhci_readl(host, in tegra_sdhci_set_padctrl()
545 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
563 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
[all …]
Dsdhci.c58 sdhci_readl(host, SDHCI_DMA_ADDRESS), in sdhci_dumpregs()
64 sdhci_readl(host, SDHCI_ARGUMENT), in sdhci_dumpregs()
67 sdhci_readl(host, SDHCI_PRESENT_STATE), in sdhci_dumpregs()
77 sdhci_readl(host, SDHCI_INT_STATUS)); in sdhci_dumpregs()
79 sdhci_readl(host, SDHCI_INT_ENABLE), in sdhci_dumpregs()
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); in sdhci_dumpregs()
85 sdhci_readl(host, SDHCI_CAPABILITIES), in sdhci_dumpregs()
86 sdhci_readl(host, SDHCI_CAPABILITIES_1)); in sdhci_dumpregs()
89 sdhci_readl(host, SDHCI_MAX_CURRENT)); in sdhci_dumpregs()
91 sdhci_readl(host, SDHCI_RESPONSE), in sdhci_dumpregs()
[all …]
Dsdhci-brcmstb.c58 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_brcmstb_probe()
61 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in sdhci_brcmstb_probe()
Dsdhci-of-arasan.c242 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe()
344 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
346 sdhci_readl(host, SDHCI_BUFFER); in sdhci_arasan_cqe_enable()
347 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
Dsdhci-acpi.c371 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in bxt_get_cd()
386 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && in intel_probe_slot()
387 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) in intel_probe_slot()
832 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); in sdhci_acpi_remove()
Dsdhci-pxav3.c129 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in armada_38x_quirks()
130 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in armada_38x_quirks()
Dsdhci-esdhc-imx.c773 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
800 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
1258 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable()
1260 sdhci_readl(host, SDHCI_BUFFER); in esdhc_cqe_enable()
1261 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable()
Dsdhci.h675 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
716 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
Dsdhci-pci-core.c620 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in bxt_get_cd()
664 val = sdhci_readl(host, INTEL_HS400_ES_REG); in intel_hs400_enhanced_strobe()
866 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); in glk_rpm_retune_wa()
867 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); in glk_rpm_retune_wa()