1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/acpi.h>
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/pinctrl/pinctrl.h>
11 
12 #include "pinctrl-msm.h"
13 
14 #define FUNCTION(fname)					\
15 	[msm_mux_##fname] = {				\
16 		.name = #fname,				\
17 		.groups = fname##_groups,		\
18 		.ngroups = ARRAY_SIZE(fname##_groups),	\
19 	}
20 
21 #define NORTH	0x00500000
22 #define SOUTH	0x00900000
23 #define EAST	0x00100000
24 #define REG_SIZE 0x1000
25 #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10)	\
26 	{						\
27 		.name = "gpio" #id,			\
28 		.pins = gpio##id##_pins,		\
29 		.npins = ARRAY_SIZE(gpio##id##_pins),	\
30 		.funcs = (int[]){			\
31 			msm_mux_gpio, /* gpio mode */	\
32 			msm_mux_##f1,			\
33 			msm_mux_##f2,			\
34 			msm_mux_##f3,			\
35 			msm_mux_##f4,			\
36 			msm_mux_##f5,			\
37 			msm_mux_##f6,			\
38 			msm_mux_##f7,			\
39 			msm_mux_##f8,			\
40 			msm_mux_##f9,			\
41 			msm_mux_##f10			\
42 		},					\
43 		.nfuncs = 11,				\
44 		.ctl_reg = base + REG_SIZE * id,		\
45 		.io_reg = base + 0x4 + REG_SIZE * id,		\
46 		.intr_cfg_reg = base + 0x8 + REG_SIZE * id,	\
47 		.intr_status_reg = base + 0xc + REG_SIZE * id,	\
48 		.intr_target_reg = base + 0x8 + REG_SIZE * id,	\
49 		.mux_bit = 2,			\
50 		.pull_bit = 0,			\
51 		.drv_bit = 6,			\
52 		.oe_bit = 9,			\
53 		.in_bit = 0,			\
54 		.out_bit = 1,			\
55 		.intr_enable_bit = 0,		\
56 		.intr_status_bit = 0,		\
57 		.intr_target_bit = 5,		\
58 		.intr_target_kpss_val = 3,	\
59 		.intr_raw_status_bit = 4,	\
60 		.intr_polarity_bit = 1,		\
61 		.intr_detection_bit = 2,	\
62 		.intr_detection_width = 2,	\
63 	}
64 
65 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)	\
66 	{						\
67 		.name = #pg_name,			\
68 		.pins = pg_name##_pins,			\
69 		.npins = ARRAY_SIZE(pg_name##_pins),	\
70 		.ctl_reg = ctl,				\
71 		.io_reg = 0,				\
72 		.intr_cfg_reg = 0,			\
73 		.intr_status_reg = 0,			\
74 		.intr_target_reg = 0,			\
75 		.mux_bit = -1,				\
76 		.pull_bit = pull,			\
77 		.drv_bit = drv,				\
78 		.oe_bit = -1,				\
79 		.in_bit = -1,				\
80 		.out_bit = -1,				\
81 		.intr_enable_bit = -1,			\
82 		.intr_status_bit = -1,			\
83 		.intr_target_bit = -1,			\
84 		.intr_raw_status_bit = -1,		\
85 		.intr_polarity_bit = -1,		\
86 		.intr_detection_bit = -1,		\
87 		.intr_detection_width = -1,		\
88 	}
89 
90 #define UFS_RESET(pg_name, offset)				\
91 	{						\
92 		.name = #pg_name,			\
93 		.pins = pg_name##_pins,			\
94 		.npins = ARRAY_SIZE(pg_name##_pins),	\
95 		.ctl_reg = offset,			\
96 		.io_reg = offset + 0x4,			\
97 		.intr_cfg_reg = 0,			\
98 		.intr_status_reg = 0,			\
99 		.intr_target_reg = 0,			\
100 		.mux_bit = -1,				\
101 		.pull_bit = 3,				\
102 		.drv_bit = 0,				\
103 		.oe_bit = -1,				\
104 		.in_bit = -1,				\
105 		.out_bit = 0,				\
106 		.intr_enable_bit = -1,			\
107 		.intr_status_bit = -1,			\
108 		.intr_target_bit = -1,			\
109 		.intr_raw_status_bit = -1,		\
110 		.intr_polarity_bit = -1,		\
111 		.intr_detection_bit = -1,		\
112 		.intr_detection_width = -1,		\
113 	}
114 static const struct pinctrl_pin_desc sdm845_pins[] = {
115 	PINCTRL_PIN(0, "GPIO_0"),
116 	PINCTRL_PIN(1, "GPIO_1"),
117 	PINCTRL_PIN(2, "GPIO_2"),
118 	PINCTRL_PIN(3, "GPIO_3"),
119 	PINCTRL_PIN(4, "GPIO_4"),
120 	PINCTRL_PIN(5, "GPIO_5"),
121 	PINCTRL_PIN(6, "GPIO_6"),
122 	PINCTRL_PIN(7, "GPIO_7"),
123 	PINCTRL_PIN(8, "GPIO_8"),
124 	PINCTRL_PIN(9, "GPIO_9"),
125 	PINCTRL_PIN(10, "GPIO_10"),
126 	PINCTRL_PIN(11, "GPIO_11"),
127 	PINCTRL_PIN(12, "GPIO_12"),
128 	PINCTRL_PIN(13, "GPIO_13"),
129 	PINCTRL_PIN(14, "GPIO_14"),
130 	PINCTRL_PIN(15, "GPIO_15"),
131 	PINCTRL_PIN(16, "GPIO_16"),
132 	PINCTRL_PIN(17, "GPIO_17"),
133 	PINCTRL_PIN(18, "GPIO_18"),
134 	PINCTRL_PIN(19, "GPIO_19"),
135 	PINCTRL_PIN(20, "GPIO_20"),
136 	PINCTRL_PIN(21, "GPIO_21"),
137 	PINCTRL_PIN(22, "GPIO_22"),
138 	PINCTRL_PIN(23, "GPIO_23"),
139 	PINCTRL_PIN(24, "GPIO_24"),
140 	PINCTRL_PIN(25, "GPIO_25"),
141 	PINCTRL_PIN(26, "GPIO_26"),
142 	PINCTRL_PIN(27, "GPIO_27"),
143 	PINCTRL_PIN(28, "GPIO_28"),
144 	PINCTRL_PIN(29, "GPIO_29"),
145 	PINCTRL_PIN(30, "GPIO_30"),
146 	PINCTRL_PIN(31, "GPIO_31"),
147 	PINCTRL_PIN(32, "GPIO_32"),
148 	PINCTRL_PIN(33, "GPIO_33"),
149 	PINCTRL_PIN(34, "GPIO_34"),
150 	PINCTRL_PIN(35, "GPIO_35"),
151 	PINCTRL_PIN(36, "GPIO_36"),
152 	PINCTRL_PIN(37, "GPIO_37"),
153 	PINCTRL_PIN(38, "GPIO_38"),
154 	PINCTRL_PIN(39, "GPIO_39"),
155 	PINCTRL_PIN(40, "GPIO_40"),
156 	PINCTRL_PIN(41, "GPIO_41"),
157 	PINCTRL_PIN(42, "GPIO_42"),
158 	PINCTRL_PIN(43, "GPIO_43"),
159 	PINCTRL_PIN(44, "GPIO_44"),
160 	PINCTRL_PIN(45, "GPIO_45"),
161 	PINCTRL_PIN(46, "GPIO_46"),
162 	PINCTRL_PIN(47, "GPIO_47"),
163 	PINCTRL_PIN(48, "GPIO_48"),
164 	PINCTRL_PIN(49, "GPIO_49"),
165 	PINCTRL_PIN(50, "GPIO_50"),
166 	PINCTRL_PIN(51, "GPIO_51"),
167 	PINCTRL_PIN(52, "GPIO_52"),
168 	PINCTRL_PIN(53, "GPIO_53"),
169 	PINCTRL_PIN(54, "GPIO_54"),
170 	PINCTRL_PIN(55, "GPIO_55"),
171 	PINCTRL_PIN(56, "GPIO_56"),
172 	PINCTRL_PIN(57, "GPIO_57"),
173 	PINCTRL_PIN(58, "GPIO_58"),
174 	PINCTRL_PIN(59, "GPIO_59"),
175 	PINCTRL_PIN(60, "GPIO_60"),
176 	PINCTRL_PIN(61, "GPIO_61"),
177 	PINCTRL_PIN(62, "GPIO_62"),
178 	PINCTRL_PIN(63, "GPIO_63"),
179 	PINCTRL_PIN(64, "GPIO_64"),
180 	PINCTRL_PIN(65, "GPIO_65"),
181 	PINCTRL_PIN(66, "GPIO_66"),
182 	PINCTRL_PIN(67, "GPIO_67"),
183 	PINCTRL_PIN(68, "GPIO_68"),
184 	PINCTRL_PIN(69, "GPIO_69"),
185 	PINCTRL_PIN(70, "GPIO_70"),
186 	PINCTRL_PIN(71, "GPIO_71"),
187 	PINCTRL_PIN(72, "GPIO_72"),
188 	PINCTRL_PIN(73, "GPIO_73"),
189 	PINCTRL_PIN(74, "GPIO_74"),
190 	PINCTRL_PIN(75, "GPIO_75"),
191 	PINCTRL_PIN(76, "GPIO_76"),
192 	PINCTRL_PIN(77, "GPIO_77"),
193 	PINCTRL_PIN(78, "GPIO_78"),
194 	PINCTRL_PIN(79, "GPIO_79"),
195 	PINCTRL_PIN(80, "GPIO_80"),
196 	PINCTRL_PIN(81, "GPIO_81"),
197 	PINCTRL_PIN(82, "GPIO_82"),
198 	PINCTRL_PIN(83, "GPIO_83"),
199 	PINCTRL_PIN(84, "GPIO_84"),
200 	PINCTRL_PIN(85, "GPIO_85"),
201 	PINCTRL_PIN(86, "GPIO_86"),
202 	PINCTRL_PIN(87, "GPIO_87"),
203 	PINCTRL_PIN(88, "GPIO_88"),
204 	PINCTRL_PIN(89, "GPIO_89"),
205 	PINCTRL_PIN(90, "GPIO_90"),
206 	PINCTRL_PIN(91, "GPIO_91"),
207 	PINCTRL_PIN(92, "GPIO_92"),
208 	PINCTRL_PIN(93, "GPIO_93"),
209 	PINCTRL_PIN(94, "GPIO_94"),
210 	PINCTRL_PIN(95, "GPIO_95"),
211 	PINCTRL_PIN(96, "GPIO_96"),
212 	PINCTRL_PIN(97, "GPIO_97"),
213 	PINCTRL_PIN(98, "GPIO_98"),
214 	PINCTRL_PIN(99, "GPIO_99"),
215 	PINCTRL_PIN(100, "GPIO_100"),
216 	PINCTRL_PIN(101, "GPIO_101"),
217 	PINCTRL_PIN(102, "GPIO_102"),
218 	PINCTRL_PIN(103, "GPIO_103"),
219 	PINCTRL_PIN(104, "GPIO_104"),
220 	PINCTRL_PIN(105, "GPIO_105"),
221 	PINCTRL_PIN(106, "GPIO_106"),
222 	PINCTRL_PIN(107, "GPIO_107"),
223 	PINCTRL_PIN(108, "GPIO_108"),
224 	PINCTRL_PIN(109, "GPIO_109"),
225 	PINCTRL_PIN(110, "GPIO_110"),
226 	PINCTRL_PIN(111, "GPIO_111"),
227 	PINCTRL_PIN(112, "GPIO_112"),
228 	PINCTRL_PIN(113, "GPIO_113"),
229 	PINCTRL_PIN(114, "GPIO_114"),
230 	PINCTRL_PIN(115, "GPIO_115"),
231 	PINCTRL_PIN(116, "GPIO_116"),
232 	PINCTRL_PIN(117, "GPIO_117"),
233 	PINCTRL_PIN(118, "GPIO_118"),
234 	PINCTRL_PIN(119, "GPIO_119"),
235 	PINCTRL_PIN(120, "GPIO_120"),
236 	PINCTRL_PIN(121, "GPIO_121"),
237 	PINCTRL_PIN(122, "GPIO_122"),
238 	PINCTRL_PIN(123, "GPIO_123"),
239 	PINCTRL_PIN(124, "GPIO_124"),
240 	PINCTRL_PIN(125, "GPIO_125"),
241 	PINCTRL_PIN(126, "GPIO_126"),
242 	PINCTRL_PIN(127, "GPIO_127"),
243 	PINCTRL_PIN(128, "GPIO_128"),
244 	PINCTRL_PIN(129, "GPIO_129"),
245 	PINCTRL_PIN(130, "GPIO_130"),
246 	PINCTRL_PIN(131, "GPIO_131"),
247 	PINCTRL_PIN(132, "GPIO_132"),
248 	PINCTRL_PIN(133, "GPIO_133"),
249 	PINCTRL_PIN(134, "GPIO_134"),
250 	PINCTRL_PIN(135, "GPIO_135"),
251 	PINCTRL_PIN(136, "GPIO_136"),
252 	PINCTRL_PIN(137, "GPIO_137"),
253 	PINCTRL_PIN(138, "GPIO_138"),
254 	PINCTRL_PIN(139, "GPIO_139"),
255 	PINCTRL_PIN(140, "GPIO_140"),
256 	PINCTRL_PIN(141, "GPIO_141"),
257 	PINCTRL_PIN(142, "GPIO_142"),
258 	PINCTRL_PIN(143, "GPIO_143"),
259 	PINCTRL_PIN(144, "GPIO_144"),
260 	PINCTRL_PIN(145, "GPIO_145"),
261 	PINCTRL_PIN(146, "GPIO_146"),
262 	PINCTRL_PIN(147, "GPIO_147"),
263 	PINCTRL_PIN(148, "GPIO_148"),
264 	PINCTRL_PIN(149, "GPIO_149"),
265 	PINCTRL_PIN(150, "UFS_RESET"),
266 	PINCTRL_PIN(151, "SDC2_CLK"),
267 	PINCTRL_PIN(152, "SDC2_CMD"),
268 	PINCTRL_PIN(153, "SDC2_DATA"),
269 };
270 
271 #define DECLARE_MSM_GPIO_PINS(pin) \
272 	static const unsigned int gpio##pin##_pins[] = { pin }
273 DECLARE_MSM_GPIO_PINS(0);
274 DECLARE_MSM_GPIO_PINS(1);
275 DECLARE_MSM_GPIO_PINS(2);
276 DECLARE_MSM_GPIO_PINS(3);
277 DECLARE_MSM_GPIO_PINS(4);
278 DECLARE_MSM_GPIO_PINS(5);
279 DECLARE_MSM_GPIO_PINS(6);
280 DECLARE_MSM_GPIO_PINS(7);
281 DECLARE_MSM_GPIO_PINS(8);
282 DECLARE_MSM_GPIO_PINS(9);
283 DECLARE_MSM_GPIO_PINS(10);
284 DECLARE_MSM_GPIO_PINS(11);
285 DECLARE_MSM_GPIO_PINS(12);
286 DECLARE_MSM_GPIO_PINS(13);
287 DECLARE_MSM_GPIO_PINS(14);
288 DECLARE_MSM_GPIO_PINS(15);
289 DECLARE_MSM_GPIO_PINS(16);
290 DECLARE_MSM_GPIO_PINS(17);
291 DECLARE_MSM_GPIO_PINS(18);
292 DECLARE_MSM_GPIO_PINS(19);
293 DECLARE_MSM_GPIO_PINS(20);
294 DECLARE_MSM_GPIO_PINS(21);
295 DECLARE_MSM_GPIO_PINS(22);
296 DECLARE_MSM_GPIO_PINS(23);
297 DECLARE_MSM_GPIO_PINS(24);
298 DECLARE_MSM_GPIO_PINS(25);
299 DECLARE_MSM_GPIO_PINS(26);
300 DECLARE_MSM_GPIO_PINS(27);
301 DECLARE_MSM_GPIO_PINS(28);
302 DECLARE_MSM_GPIO_PINS(29);
303 DECLARE_MSM_GPIO_PINS(30);
304 DECLARE_MSM_GPIO_PINS(31);
305 DECLARE_MSM_GPIO_PINS(32);
306 DECLARE_MSM_GPIO_PINS(33);
307 DECLARE_MSM_GPIO_PINS(34);
308 DECLARE_MSM_GPIO_PINS(35);
309 DECLARE_MSM_GPIO_PINS(36);
310 DECLARE_MSM_GPIO_PINS(37);
311 DECLARE_MSM_GPIO_PINS(38);
312 DECLARE_MSM_GPIO_PINS(39);
313 DECLARE_MSM_GPIO_PINS(40);
314 DECLARE_MSM_GPIO_PINS(41);
315 DECLARE_MSM_GPIO_PINS(42);
316 DECLARE_MSM_GPIO_PINS(43);
317 DECLARE_MSM_GPIO_PINS(44);
318 DECLARE_MSM_GPIO_PINS(45);
319 DECLARE_MSM_GPIO_PINS(46);
320 DECLARE_MSM_GPIO_PINS(47);
321 DECLARE_MSM_GPIO_PINS(48);
322 DECLARE_MSM_GPIO_PINS(49);
323 DECLARE_MSM_GPIO_PINS(50);
324 DECLARE_MSM_GPIO_PINS(51);
325 DECLARE_MSM_GPIO_PINS(52);
326 DECLARE_MSM_GPIO_PINS(53);
327 DECLARE_MSM_GPIO_PINS(54);
328 DECLARE_MSM_GPIO_PINS(55);
329 DECLARE_MSM_GPIO_PINS(56);
330 DECLARE_MSM_GPIO_PINS(57);
331 DECLARE_MSM_GPIO_PINS(58);
332 DECLARE_MSM_GPIO_PINS(59);
333 DECLARE_MSM_GPIO_PINS(60);
334 DECLARE_MSM_GPIO_PINS(61);
335 DECLARE_MSM_GPIO_PINS(62);
336 DECLARE_MSM_GPIO_PINS(63);
337 DECLARE_MSM_GPIO_PINS(64);
338 DECLARE_MSM_GPIO_PINS(65);
339 DECLARE_MSM_GPIO_PINS(66);
340 DECLARE_MSM_GPIO_PINS(67);
341 DECLARE_MSM_GPIO_PINS(68);
342 DECLARE_MSM_GPIO_PINS(69);
343 DECLARE_MSM_GPIO_PINS(70);
344 DECLARE_MSM_GPIO_PINS(71);
345 DECLARE_MSM_GPIO_PINS(72);
346 DECLARE_MSM_GPIO_PINS(73);
347 DECLARE_MSM_GPIO_PINS(74);
348 DECLARE_MSM_GPIO_PINS(75);
349 DECLARE_MSM_GPIO_PINS(76);
350 DECLARE_MSM_GPIO_PINS(77);
351 DECLARE_MSM_GPIO_PINS(78);
352 DECLARE_MSM_GPIO_PINS(79);
353 DECLARE_MSM_GPIO_PINS(80);
354 DECLARE_MSM_GPIO_PINS(81);
355 DECLARE_MSM_GPIO_PINS(82);
356 DECLARE_MSM_GPIO_PINS(83);
357 DECLARE_MSM_GPIO_PINS(84);
358 DECLARE_MSM_GPIO_PINS(85);
359 DECLARE_MSM_GPIO_PINS(86);
360 DECLARE_MSM_GPIO_PINS(87);
361 DECLARE_MSM_GPIO_PINS(88);
362 DECLARE_MSM_GPIO_PINS(89);
363 DECLARE_MSM_GPIO_PINS(90);
364 DECLARE_MSM_GPIO_PINS(91);
365 DECLARE_MSM_GPIO_PINS(92);
366 DECLARE_MSM_GPIO_PINS(93);
367 DECLARE_MSM_GPIO_PINS(94);
368 DECLARE_MSM_GPIO_PINS(95);
369 DECLARE_MSM_GPIO_PINS(96);
370 DECLARE_MSM_GPIO_PINS(97);
371 DECLARE_MSM_GPIO_PINS(98);
372 DECLARE_MSM_GPIO_PINS(99);
373 DECLARE_MSM_GPIO_PINS(100);
374 DECLARE_MSM_GPIO_PINS(101);
375 DECLARE_MSM_GPIO_PINS(102);
376 DECLARE_MSM_GPIO_PINS(103);
377 DECLARE_MSM_GPIO_PINS(104);
378 DECLARE_MSM_GPIO_PINS(105);
379 DECLARE_MSM_GPIO_PINS(106);
380 DECLARE_MSM_GPIO_PINS(107);
381 DECLARE_MSM_GPIO_PINS(108);
382 DECLARE_MSM_GPIO_PINS(109);
383 DECLARE_MSM_GPIO_PINS(110);
384 DECLARE_MSM_GPIO_PINS(111);
385 DECLARE_MSM_GPIO_PINS(112);
386 DECLARE_MSM_GPIO_PINS(113);
387 DECLARE_MSM_GPIO_PINS(114);
388 DECLARE_MSM_GPIO_PINS(115);
389 DECLARE_MSM_GPIO_PINS(116);
390 DECLARE_MSM_GPIO_PINS(117);
391 DECLARE_MSM_GPIO_PINS(118);
392 DECLARE_MSM_GPIO_PINS(119);
393 DECLARE_MSM_GPIO_PINS(120);
394 DECLARE_MSM_GPIO_PINS(121);
395 DECLARE_MSM_GPIO_PINS(122);
396 DECLARE_MSM_GPIO_PINS(123);
397 DECLARE_MSM_GPIO_PINS(124);
398 DECLARE_MSM_GPIO_PINS(125);
399 DECLARE_MSM_GPIO_PINS(126);
400 DECLARE_MSM_GPIO_PINS(127);
401 DECLARE_MSM_GPIO_PINS(128);
402 DECLARE_MSM_GPIO_PINS(129);
403 DECLARE_MSM_GPIO_PINS(130);
404 DECLARE_MSM_GPIO_PINS(131);
405 DECLARE_MSM_GPIO_PINS(132);
406 DECLARE_MSM_GPIO_PINS(133);
407 DECLARE_MSM_GPIO_PINS(134);
408 DECLARE_MSM_GPIO_PINS(135);
409 DECLARE_MSM_GPIO_PINS(136);
410 DECLARE_MSM_GPIO_PINS(137);
411 DECLARE_MSM_GPIO_PINS(138);
412 DECLARE_MSM_GPIO_PINS(139);
413 DECLARE_MSM_GPIO_PINS(140);
414 DECLARE_MSM_GPIO_PINS(141);
415 DECLARE_MSM_GPIO_PINS(142);
416 DECLARE_MSM_GPIO_PINS(143);
417 DECLARE_MSM_GPIO_PINS(144);
418 DECLARE_MSM_GPIO_PINS(145);
419 DECLARE_MSM_GPIO_PINS(146);
420 DECLARE_MSM_GPIO_PINS(147);
421 DECLARE_MSM_GPIO_PINS(148);
422 DECLARE_MSM_GPIO_PINS(149);
423 
424 static const unsigned int ufs_reset_pins[] = { 150 };
425 static const unsigned int sdc2_clk_pins[] = { 151 };
426 static const unsigned int sdc2_cmd_pins[] = { 152 };
427 static const unsigned int sdc2_data_pins[] = { 153 };
428 
429 enum sdm845_functions {
430 	msm_mux_gpio,
431 	msm_mux_adsp_ext,
432 	msm_mux_agera_pll,
433 	msm_mux_atest_char,
434 	msm_mux_atest_tsens,
435 	msm_mux_atest_tsens2,
436 	msm_mux_atest_usb1,
437 	msm_mux_atest_usb10,
438 	msm_mux_atest_usb11,
439 	msm_mux_atest_usb12,
440 	msm_mux_atest_usb13,
441 	msm_mux_atest_usb2,
442 	msm_mux_atest_usb20,
443 	msm_mux_atest_usb21,
444 	msm_mux_atest_usb22,
445 	msm_mux_atest_usb23,
446 	msm_mux_audio_ref,
447 	msm_mux_btfm_slimbus,
448 	msm_mux_cam_mclk,
449 	msm_mux_cci_async,
450 	msm_mux_cci_i2c,
451 	msm_mux_cci_timer0,
452 	msm_mux_cci_timer1,
453 	msm_mux_cci_timer2,
454 	msm_mux_cci_timer3,
455 	msm_mux_cci_timer4,
456 	msm_mux_cri_trng,
457 	msm_mux_cri_trng0,
458 	msm_mux_cri_trng1,
459 	msm_mux_dbg_out,
460 	msm_mux_ddr_bist,
461 	msm_mux_ddr_pxi0,
462 	msm_mux_ddr_pxi1,
463 	msm_mux_ddr_pxi2,
464 	msm_mux_ddr_pxi3,
465 	msm_mux_edp_hot,
466 	msm_mux_edp_lcd,
467 	msm_mux_gcc_gp1,
468 	msm_mux_gcc_gp2,
469 	msm_mux_gcc_gp3,
470 	msm_mux_jitter_bist,
471 	msm_mux_ldo_en,
472 	msm_mux_ldo_update,
473 	msm_mux_lpass_slimbus,
474 	msm_mux_m_voc,
475 	msm_mux_mdp_vsync,
476 	msm_mux_mdp_vsync0,
477 	msm_mux_mdp_vsync1,
478 	msm_mux_mdp_vsync2,
479 	msm_mux_mdp_vsync3,
480 	msm_mux_mss_lte,
481 	msm_mux_nav_pps,
482 	msm_mux_pa_indicator,
483 	msm_mux_pci_e0,
484 	msm_mux_pci_e1,
485 	msm_mux_phase_flag,
486 	msm_mux_pll_bist,
487 	msm_mux_pll_bypassnl,
488 	msm_mux_pll_reset,
489 	msm_mux_pri_mi2s,
490 	msm_mux_pri_mi2s_ws,
491 	msm_mux_prng_rosc,
492 	msm_mux_qdss_cti,
493 	msm_mux_qdss,
494 	msm_mux_qlink_enable,
495 	msm_mux_qlink_request,
496 	msm_mux_qspi_clk,
497 	msm_mux_qspi_cs,
498 	msm_mux_qspi_data,
499 	msm_mux_qua_mi2s,
500 	msm_mux_qup0,
501 	msm_mux_qup1,
502 	msm_mux_qup10,
503 	msm_mux_qup11,
504 	msm_mux_qup12,
505 	msm_mux_qup13,
506 	msm_mux_qup14,
507 	msm_mux_qup15,
508 	msm_mux_qup2,
509 	msm_mux_qup3,
510 	msm_mux_qup4,
511 	msm_mux_qup5,
512 	msm_mux_qup6,
513 	msm_mux_qup7,
514 	msm_mux_qup8,
515 	msm_mux_qup9,
516 	msm_mux_qup_l4,
517 	msm_mux_qup_l5,
518 	msm_mux_qup_l6,
519 	msm_mux_sd_write,
520 	msm_mux_sdc4_clk,
521 	msm_mux_sdc4_cmd,
522 	msm_mux_sdc4_data,
523 	msm_mux_sec_mi2s,
524 	msm_mux_sp_cmu,
525 	msm_mux_spkr_i2s,
526 	msm_mux_ter_mi2s,
527 	msm_mux_tgu_ch0,
528 	msm_mux_tgu_ch1,
529 	msm_mux_tgu_ch2,
530 	msm_mux_tgu_ch3,
531 	msm_mux_tsense_pwm1,
532 	msm_mux_tsense_pwm2,
533 	msm_mux_tsif1_clk,
534 	msm_mux_tsif1_data,
535 	msm_mux_tsif1_en,
536 	msm_mux_tsif1_error,
537 	msm_mux_tsif1_sync,
538 	msm_mux_tsif2_clk,
539 	msm_mux_tsif2_data,
540 	msm_mux_tsif2_en,
541 	msm_mux_tsif2_error,
542 	msm_mux_tsif2_sync,
543 	msm_mux_uim1_clk,
544 	msm_mux_uim1_data,
545 	msm_mux_uim1_present,
546 	msm_mux_uim1_reset,
547 	msm_mux_uim2_clk,
548 	msm_mux_uim2_data,
549 	msm_mux_uim2_present,
550 	msm_mux_uim2_reset,
551 	msm_mux_uim_batt,
552 	msm_mux_usb_phy,
553 	msm_mux_vfr_1,
554 	msm_mux_vsense_trigger,
555 	msm_mux_wlan1_adc0,
556 	msm_mux_wlan1_adc1,
557 	msm_mux_wlan2_adc0,
558 	msm_mux_wlan2_adc1,
559 	msm_mux__,
560 };
561 
562 static const char * const ddr_pxi3_groups[] = {
563 	"gpio12", "gpio13",
564 };
565 static const char * const cam_mclk_groups[] = {
566 	"gpio13", "gpio14", "gpio15", "gpio16",
567 };
568 static const char * const pll_bypassnl_groups[] = {
569 	"gpio13",
570 };
571 static const char * const qdss_groups[] = {
572 	"gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
573 	"gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
574 	"gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
575 	"gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
576 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
577 	"gpio123", "gpio124",
578 };
579 static const char * const pll_reset_groups[] = {
580 	"gpio14",
581 };
582 static const char * const cci_i2c_groups[] = {
583 	"gpio17", "gpio18", "gpio19", "gpio20",
584 };
585 static const char * const qup1_groups[] = {
586 	"gpio17", "gpio18", "gpio19", "gpio20",
587 };
588 static const char * const cci_timer0_groups[] = {
589 	"gpio21",
590 };
591 static const char * const gcc_gp2_groups[] = {
592 	"gpio21", "gpio58",
593 };
594 static const char * const cci_timer1_groups[] = {
595 	"gpio22",
596 };
597 static const char * const gcc_gp3_groups[] = {
598 	"gpio22", "gpio59",
599 };
600 static const char * const cci_timer2_groups[] = {
601 	"gpio23",
602 };
603 static const char * const cci_timer3_groups[] = {
604 	"gpio24",
605 };
606 static const char * const cci_async_groups[] = {
607 	"gpio24", "gpio25", "gpio26",
608 };
609 static const char * const cci_timer4_groups[] = {
610 	"gpio25",
611 };
612 static const char * const qup2_groups[] = {
613 	"gpio27", "gpio28", "gpio29", "gpio30",
614 };
615 static const char * const phase_flag_groups[] = {
616 	"gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
617 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
618 	"gpio64", "gpio74", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90",
619 	"gpio96", "gpio99", "gpio100", "gpio103", "gpio137", "gpio138",
620 	"gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
621 };
622 static const char * const qup11_groups[] = {
623 	"gpio31", "gpio32", "gpio33", "gpio34",
624 };
625 static const char * const qup14_groups[] = {
626 	"gpio31", "gpio32", "gpio33", "gpio34",
627 };
628 static const char * const pci_e0_groups[] = {
629 	"gpio35", "gpio36",
630 };
631 static const char * const jitter_bist_groups[] = {
632 	"gpio35",
633 };
634 static const char * const pll_bist_groups[] = {
635 	"gpio36",
636 };
637 static const char * const atest_tsens_groups[] = {
638 	"gpio36",
639 };
640 static const char * const agera_pll_groups[] = {
641 	"gpio37",
642 };
643 static const char * const usb_phy_groups[] = {
644 	"gpio38",
645 };
646 static const char * const lpass_slimbus_groups[] = {
647 	"gpio39", "gpio70", "gpio71", "gpio72",
648 };
649 static const char * const sd_write_groups[] = {
650 	"gpio40",
651 };
652 static const char * const tsif1_error_groups[] = {
653 	"gpio40",
654 };
655 static const char * const qup3_groups[] = {
656 	"gpio41", "gpio42", "gpio43", "gpio44",
657 };
658 static const char * const qup6_groups[] = {
659 	"gpio45", "gpio46", "gpio47", "gpio48",
660 };
661 static const char * const qup12_groups[] = {
662 	"gpio49", "gpio50", "gpio51", "gpio52",
663 };
664 static const char * const qup10_groups[] = {
665 	"gpio53", "gpio54", "gpio55", "gpio56",
666 };
667 static const char * const qua_mi2s_groups[] = {
668 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
669 };
670 static const char * const gcc_gp1_groups[] = {
671 	"gpio57", "gpio78",
672 };
673 static const char * const cri_trng0_groups[] = {
674 	"gpio60",
675 };
676 static const char * const cri_trng1_groups[] = {
677 	"gpio61",
678 };
679 static const char * const cri_trng_groups[] = {
680 	"gpio62",
681 };
682 static const char * const pri_mi2s_groups[] = {
683 	"gpio64", "gpio65", "gpio67", "gpio68",
684 };
685 static const char * const sp_cmu_groups[] = {
686 	"gpio64",
687 };
688 static const char * const qup8_groups[] = {
689 	"gpio65", "gpio66", "gpio67", "gpio68",
690 };
691 static const char * const pri_mi2s_ws_groups[] = {
692 	"gpio66",
693 };
694 static const char * const spkr_i2s_groups[] = {
695 	"gpio69", "gpio70", "gpio71", "gpio72",
696 };
697 static const char * const audio_ref_groups[] = {
698 	"gpio69",
699 };
700 static const char * const tsense_pwm1_groups[] = {
701 	"gpio71",
702 };
703 static const char * const tsense_pwm2_groups[] = {
704 	"gpio71",
705 };
706 static const char * const btfm_slimbus_groups[] = {
707 	"gpio73", "gpio74",
708 };
709 static const char * const atest_usb2_groups[] = {
710 	"gpio73",
711 };
712 static const char * const ter_mi2s_groups[] = {
713 	"gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
714 };
715 static const char * const atest_usb23_groups[] = {
716 	"gpio74",
717 };
718 static const char * const atest_usb22_groups[] = {
719 	"gpio75",
720 };
721 static const char * const atest_usb21_groups[] = {
722 	"gpio76",
723 };
724 static const char * const atest_usb20_groups[] = {
725 	"gpio77",
726 };
727 static const char * const sec_mi2s_groups[] = {
728 	"gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
729 };
730 static const char * const qup15_groups[] = {
731 	"gpio81", "gpio82", "gpio83", "gpio84",
732 };
733 static const char * const qup5_groups[] = {
734 	"gpio85", "gpio86", "gpio87", "gpio88",
735 };
736 static const char * const tsif1_clk_groups[] = {
737 	"gpio89",
738 };
739 static const char * const qup4_groups[] = {
740 	"gpio89", "gpio90", "gpio91", "gpio92",
741 };
742 static const char * const qspi_cs_groups[] = {
743 	"gpio89", "gpio90",
744 };
745 static const char * const tgu_ch3_groups[] = {
746 	"gpio89",
747 };
748 static const char * const tsif1_en_groups[] = {
749 	"gpio90",
750 };
751 static const char * const mdp_vsync0_groups[] = {
752 	"gpio90",
753 };
754 static const char * const mdp_vsync1_groups[] = {
755 	"gpio90",
756 };
757 static const char * const mdp_vsync2_groups[] = {
758 	"gpio90",
759 };
760 static const char * const mdp_vsync3_groups[] = {
761 	"gpio90",
762 };
763 static const char * const tgu_ch0_groups[] = {
764 	"gpio90",
765 };
766 static const char * const tsif1_data_groups[] = {
767 	"gpio91",
768 };
769 static const char * const sdc4_cmd_groups[] = {
770 	"gpio91",
771 };
772 static const char * const qspi_data_groups[] = {
773 	"gpio91", "gpio92", "gpio93", "gpio94",
774 };
775 static const char * const tgu_ch1_groups[] = {
776 	"gpio91",
777 };
778 static const char * const tsif2_error_groups[] = {
779 	"gpio92",
780 };
781 static const char * const sdc4_data_groups[] = {
782 	"gpio92",
783 	"gpio94",
784 	"gpio95",
785 	"gpio96",
786 };
787 static const char * const vfr_1_groups[] = {
788 	"gpio92",
789 };
790 static const char * const tgu_ch2_groups[] = {
791 	"gpio92",
792 };
793 static const char * const tsif2_clk_groups[] = {
794 	"gpio93",
795 };
796 static const char * const sdc4_clk_groups[] = {
797 	"gpio93",
798 };
799 static const char * const qup7_groups[] = {
800 	"gpio93", "gpio94", "gpio95", "gpio96",
801 };
802 static const char * const tsif2_en_groups[] = {
803 	"gpio94",
804 };
805 static const char * const tsif2_data_groups[] = {
806 	"gpio95",
807 };
808 static const char * const qspi_clk_groups[] = {
809 	"gpio95",
810 };
811 static const char * const tsif2_sync_groups[] = {
812 	"gpio96",
813 };
814 static const char * const ldo_en_groups[] = {
815 	"gpio97",
816 };
817 static const char * const ldo_update_groups[] = {
818 	"gpio98",
819 };
820 static const char * const pci_e1_groups[] = {
821 	"gpio102", "gpio103",
822 };
823 static const char * const prng_rosc_groups[] = {
824 	"gpio102",
825 };
826 static const char * const uim2_data_groups[] = {
827 	"gpio105",
828 };
829 static const char * const qup13_groups[] = {
830 	"gpio105", "gpio106", "gpio107", "gpio108",
831 };
832 static const char * const uim2_clk_groups[] = {
833 	"gpio106",
834 };
835 static const char * const uim2_reset_groups[] = {
836 	"gpio107",
837 };
838 static const char * const uim2_present_groups[] = {
839 	"gpio108",
840 };
841 static const char * const uim1_data_groups[] = {
842 	"gpio109",
843 };
844 static const char * const uim1_clk_groups[] = {
845 	"gpio110",
846 };
847 static const char * const uim1_reset_groups[] = {
848 	"gpio111",
849 };
850 static const char * const uim1_present_groups[] = {
851 	"gpio112",
852 };
853 static const char * const uim_batt_groups[] = {
854 	"gpio113",
855 };
856 static const char * const edp_hot_groups[] = {
857 	"gpio113",
858 };
859 static const char * const nav_pps_groups[] = {
860 	"gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128",
861 	"gpio129", "gpio129", "gpio143", "gpio143",
862 };
863 static const char * const atest_char_groups[] = {
864 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
865 };
866 static const char * const adsp_ext_groups[] = {
867 	"gpio118",
868 };
869 static const char * const qlink_request_groups[] = {
870 	"gpio130",
871 };
872 static const char * const qlink_enable_groups[] = {
873 	"gpio131",
874 };
875 static const char * const pa_indicator_groups[] = {
876 	"gpio135",
877 };
878 static const char * const mss_lte_groups[] = {
879 	"gpio144", "gpio145",
880 };
881 static const char * const qup0_groups[] = {
882 	"gpio0", "gpio1", "gpio2", "gpio3",
883 };
884 static const char * const gpio_groups[] = {
885 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
886 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
887 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
888 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
889 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
890 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
891 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
892 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
893 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
894 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
895 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
896 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
897 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
898 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
899 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
900 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
901 	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
902 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
903 	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
904 	"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
905 	"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
906 	"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
907 	"gpio147", "gpio148", "gpio149",
908 };
909 static const char * const qup9_groups[] = {
910 	"gpio4", "gpio5", "gpio6", "gpio7",
911 };
912 static const char * const qdss_cti_groups[] = {
913 	"gpio4", "gpio5", "gpio51", "gpio52", "gpio62", "gpio63", "gpio90",
914 	"gpio91",
915 };
916 static const char * const ddr_pxi0_groups[] = {
917 	"gpio6", "gpio7",
918 };
919 static const char * const ddr_bist_groups[] = {
920 	"gpio7", "gpio8", "gpio9", "gpio10",
921 };
922 static const char * const atest_tsens2_groups[] = {
923 	"gpio7",
924 };
925 static const char * const vsense_trigger_groups[] = {
926 	"gpio7",
927 };
928 static const char * const atest_usb1_groups[] = {
929 	"gpio7",
930 };
931 static const char * const qup_l4_groups[] = {
932 	"gpio8", "gpio35", "gpio105", "gpio123",
933 };
934 static const char * const wlan1_adc1_groups[] = {
935 	"gpio8",
936 };
937 static const char * const atest_usb13_groups[] = {
938 	"gpio8",
939 };
940 static const char * const ddr_pxi1_groups[] = {
941 	"gpio8", "gpio9",
942 };
943 static const char * const qup_l5_groups[] = {
944 	"gpio9", "gpio36", "gpio106", "gpio124",
945 };
946 static const char * const wlan1_adc0_groups[] = {
947 	"gpio9",
948 };
949 static const char * const atest_usb12_groups[] = {
950 	"gpio9",
951 };
952 static const char * const mdp_vsync_groups[] = {
953 	"gpio10", "gpio11", "gpio12", "gpio97", "gpio98",
954 };
955 static const char * const qup_l6_groups[] = {
956 	"gpio10", "gpio37", "gpio107", "gpio125",
957 };
958 static const char * const wlan2_adc1_groups[] = {
959 	"gpio10",
960 };
961 static const char * const atest_usb11_groups[] = {
962 	"gpio10",
963 };
964 static const char * const ddr_pxi2_groups[] = {
965 	"gpio10", "gpio11",
966 };
967 static const char * const edp_lcd_groups[] = {
968 	"gpio11",
969 };
970 static const char * const dbg_out_groups[] = {
971 	"gpio11",
972 };
973 static const char * const wlan2_adc0_groups[] = {
974 	"gpio11",
975 };
976 static const char * const atest_usb10_groups[] = {
977 	"gpio11",
978 };
979 static const char * const m_voc_groups[] = {
980 	"gpio12",
981 };
982 static const char * const tsif1_sync_groups[] = {
983 	"gpio12",
984 };
985 
986 static const struct msm_function sdm845_functions[] = {
987 	FUNCTION(gpio),
988 	FUNCTION(adsp_ext),
989 	FUNCTION(agera_pll),
990 	FUNCTION(atest_char),
991 	FUNCTION(atest_tsens),
992 	FUNCTION(atest_tsens2),
993 	FUNCTION(atest_usb1),
994 	FUNCTION(atest_usb10),
995 	FUNCTION(atest_usb11),
996 	FUNCTION(atest_usb12),
997 	FUNCTION(atest_usb13),
998 	FUNCTION(atest_usb2),
999 	FUNCTION(atest_usb20),
1000 	FUNCTION(atest_usb21),
1001 	FUNCTION(atest_usb22),
1002 	FUNCTION(atest_usb23),
1003 	FUNCTION(audio_ref),
1004 	FUNCTION(btfm_slimbus),
1005 	FUNCTION(cam_mclk),
1006 	FUNCTION(cci_async),
1007 	FUNCTION(cci_i2c),
1008 	FUNCTION(cci_timer0),
1009 	FUNCTION(cci_timer1),
1010 	FUNCTION(cci_timer2),
1011 	FUNCTION(cci_timer3),
1012 	FUNCTION(cci_timer4),
1013 	FUNCTION(cri_trng),
1014 	FUNCTION(cri_trng0),
1015 	FUNCTION(cri_trng1),
1016 	FUNCTION(dbg_out),
1017 	FUNCTION(ddr_bist),
1018 	FUNCTION(ddr_pxi0),
1019 	FUNCTION(ddr_pxi1),
1020 	FUNCTION(ddr_pxi2),
1021 	FUNCTION(ddr_pxi3),
1022 	FUNCTION(edp_hot),
1023 	FUNCTION(edp_lcd),
1024 	FUNCTION(gcc_gp1),
1025 	FUNCTION(gcc_gp2),
1026 	FUNCTION(gcc_gp3),
1027 	FUNCTION(jitter_bist),
1028 	FUNCTION(ldo_en),
1029 	FUNCTION(ldo_update),
1030 	FUNCTION(lpass_slimbus),
1031 	FUNCTION(m_voc),
1032 	FUNCTION(mdp_vsync),
1033 	FUNCTION(mdp_vsync0),
1034 	FUNCTION(mdp_vsync1),
1035 	FUNCTION(mdp_vsync2),
1036 	FUNCTION(mdp_vsync3),
1037 	FUNCTION(mss_lte),
1038 	FUNCTION(nav_pps),
1039 	FUNCTION(pa_indicator),
1040 	FUNCTION(pci_e0),
1041 	FUNCTION(pci_e1),
1042 	FUNCTION(phase_flag),
1043 	FUNCTION(pll_bist),
1044 	FUNCTION(pll_bypassnl),
1045 	FUNCTION(pll_reset),
1046 	FUNCTION(pri_mi2s),
1047 	FUNCTION(pri_mi2s_ws),
1048 	FUNCTION(prng_rosc),
1049 	FUNCTION(qdss_cti),
1050 	FUNCTION(qdss),
1051 	FUNCTION(qlink_enable),
1052 	FUNCTION(qlink_request),
1053 	FUNCTION(qspi_clk),
1054 	FUNCTION(qspi_cs),
1055 	FUNCTION(qspi_data),
1056 	FUNCTION(qua_mi2s),
1057 	FUNCTION(qup0),
1058 	FUNCTION(qup1),
1059 	FUNCTION(qup10),
1060 	FUNCTION(qup11),
1061 	FUNCTION(qup12),
1062 	FUNCTION(qup13),
1063 	FUNCTION(qup14),
1064 	FUNCTION(qup15),
1065 	FUNCTION(qup2),
1066 	FUNCTION(qup3),
1067 	FUNCTION(qup4),
1068 	FUNCTION(qup5),
1069 	FUNCTION(qup6),
1070 	FUNCTION(qup7),
1071 	FUNCTION(qup8),
1072 	FUNCTION(qup9),
1073 	FUNCTION(qup_l4),
1074 	FUNCTION(qup_l5),
1075 	FUNCTION(qup_l6),
1076 	FUNCTION(sd_write),
1077 	FUNCTION(sdc4_clk),
1078 	FUNCTION(sdc4_cmd),
1079 	FUNCTION(sdc4_data),
1080 	FUNCTION(sec_mi2s),
1081 	FUNCTION(sp_cmu),
1082 	FUNCTION(spkr_i2s),
1083 	FUNCTION(ter_mi2s),
1084 	FUNCTION(tgu_ch0),
1085 	FUNCTION(tgu_ch1),
1086 	FUNCTION(tgu_ch2),
1087 	FUNCTION(tgu_ch3),
1088 	FUNCTION(tsense_pwm1),
1089 	FUNCTION(tsense_pwm2),
1090 	FUNCTION(tsif1_clk),
1091 	FUNCTION(tsif1_data),
1092 	FUNCTION(tsif1_en),
1093 	FUNCTION(tsif1_error),
1094 	FUNCTION(tsif1_sync),
1095 	FUNCTION(tsif2_clk),
1096 	FUNCTION(tsif2_data),
1097 	FUNCTION(tsif2_en),
1098 	FUNCTION(tsif2_error),
1099 	FUNCTION(tsif2_sync),
1100 	FUNCTION(uim1_clk),
1101 	FUNCTION(uim1_data),
1102 	FUNCTION(uim1_present),
1103 	FUNCTION(uim1_reset),
1104 	FUNCTION(uim2_clk),
1105 	FUNCTION(uim2_data),
1106 	FUNCTION(uim2_present),
1107 	FUNCTION(uim2_reset),
1108 	FUNCTION(uim_batt),
1109 	FUNCTION(usb_phy),
1110 	FUNCTION(vfr_1),
1111 	FUNCTION(vsense_trigger),
1112 	FUNCTION(wlan1_adc0),
1113 	FUNCTION(wlan1_adc1),
1114 	FUNCTION(wlan2_adc0),
1115 	FUNCTION(wlan2_adc1),
1116 };
1117 
1118 /* Every pin is maintained as a single group, and missing or non-existing pin
1119  * would be maintained as dummy group to synchronize pin group index with
1120  * pin descriptor registered with pinctrl core.
1121  * Clients would not be able to request these dummy pin groups.
1122  */
1123 static const struct msm_pingroup sdm845_groups[] = {
1124 	PINGROUP(0, EAST, qup0, _, _, _, _, _, _, _, _, _),
1125 	PINGROUP(1, EAST, qup0, _, _, _, _, _, _, _, _, _),
1126 	PINGROUP(2, EAST, qup0, _, _, _, _, _, _, _, _, _),
1127 	PINGROUP(3, EAST, qup0, _, _, _, _, _, _, _, _, _),
1128 	PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
1129 	PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
1130 	PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _, _),
1131 	PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _),
1132 	PINGROUP(8, EAST, qup_l4, _, ddr_bist, _, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
1133 	PINGROUP(9, EAST, qup_l5, ddr_bist, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _, _),
1134 	PINGROUP(10, EAST, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _, _),
1135 	PINGROUP(11, EAST, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _, _),
1136 	PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _, _),
1137 	PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _, _),
1138 	PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _, _),
1139 	PINGROUP(15, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
1140 	PINGROUP(16, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
1141 	PINGROUP(17, SOUTH, cci_i2c, qup1, qdss, _, _, _, _, _, _, _),
1142 	PINGROUP(18, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1143 	PINGROUP(19, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1144 	PINGROUP(20, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1145 	PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _, _),
1146 	PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _, _),
1147 	PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _, _),
1148 	PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _, _),
1149 	PINGROUP(25, SOUTH, cci_timer4, cci_async, qdss, _, _, _, _, _, _, _),
1150 	PINGROUP(26, SOUTH, cci_async, qdss, _, _, _, _, _, _, _, _),
1151 	PINGROUP(27, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
1152 	PINGROUP(28, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
1153 	PINGROUP(29, EAST, qup2, _, phase_flag, qdss, _, _, _, _, _, _),
1154 	PINGROUP(30, EAST, qup2, phase_flag, qdss, _, _, _, _, _, _, _),
1155 	PINGROUP(31, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1156 	PINGROUP(32, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1157 	PINGROUP(33, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1158 	PINGROUP(34, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1159 	PINGROUP(35, SOUTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _, _),
1160 	PINGROUP(36, SOUTH, pci_e0, qup_l5, pll_bist, _, atest_tsens, _, _, _, _, _),
1161 	PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _, _),
1162 	PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _, _),
1163 	PINGROUP(39, EAST, lpass_slimbus, _, _, _, _, _, _, _, _, _),
1164 	PINGROUP(40, SOUTH, sd_write, tsif1_error, _, _, _, _, _, _, _, _),
1165 	PINGROUP(41, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1166 	PINGROUP(42, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1167 	PINGROUP(43, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1168 	PINGROUP(44, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1169 	PINGROUP(45, EAST, qup6, _, _, _, _, _, _, _, _, _),
1170 	PINGROUP(46, EAST, qup6, _, _, _, _, _, _, _, _, _),
1171 	PINGROUP(47, EAST, qup6, _, _, _, _, _, _, _, _, _),
1172 	PINGROUP(48, EAST, qup6, _, _, _, _, _, _, _, _, _),
1173 	PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _, _),
1174 	PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _, _),
1175 	PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _, _),
1176 	PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _, _),
1177 	PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1178 	PINGROUP(54, NORTH, qup10, _, phase_flag, _, _, _, _, _, _, _),
1179 	PINGROUP(55, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1180 	PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1181 	PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _, _),
1182 	PINGROUP(58, NORTH, qua_mi2s, gcc_gp2, phase_flag, _, _, _, _, _, _, _),
1183 	PINGROUP(59, NORTH, qua_mi2s, gcc_gp3, phase_flag, _, _, _, _, _, _, _),
1184 	PINGROUP(60, NORTH, qua_mi2s, cri_trng0, phase_flag, _, _, _, _, _, _, _),
1185 	PINGROUP(61, NORTH, qua_mi2s, cri_trng1, phase_flag, _, _, _, _, _, _, _),
1186 	PINGROUP(62, NORTH, qua_mi2s, cri_trng, phase_flag, qdss_cti, _, _, _, _, _, _),
1187 	PINGROUP(63, NORTH, qua_mi2s, _, phase_flag, qdss_cti, _, _, _, _, _, _),
1188 	PINGROUP(64, NORTH, pri_mi2s, sp_cmu, phase_flag, _, _, _, _, _, _, _),
1189 	PINGROUP(65, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1190 	PINGROUP(66, NORTH, pri_mi2s_ws, qup8, _, _, _, _, _, _, _, _),
1191 	PINGROUP(67, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1192 	PINGROUP(68, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1193 	PINGROUP(69, EAST, spkr_i2s, audio_ref, _, _, _, _, _, _, _, _),
1194 	PINGROUP(70, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
1195 	PINGROUP(71, EAST, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
1196 	PINGROUP(72, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
1197 	PINGROUP(73, EAST, btfm_slimbus, atest_usb2, _, _, _, _, _, _, _, _),
1198 	PINGROUP(74, EAST, btfm_slimbus, ter_mi2s, phase_flag, atest_usb23, _, _, _, _, _, _),
1199 	PINGROUP(75, EAST, ter_mi2s, phase_flag, qdss, atest_usb22, _, _, _, _, _, _),
1200 	PINGROUP(76, EAST, ter_mi2s, phase_flag, qdss, atest_usb21, _, _, _, _, _, _),
1201 	PINGROUP(77, EAST, ter_mi2s, phase_flag, qdss, atest_usb20, _, _, _, _, _, _),
1202 	PINGROUP(78, EAST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _, _),
1203 	PINGROUP(79, NORTH, sec_mi2s, _, _, qdss, _, _, _, _, _, _),
1204 	PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _, _),
1205 	PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1206 	PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1207 	PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1208 	PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _, _),
1209 	PINGROUP(85, EAST, qup5, _, _, _, _, _, _, _, _, _),
1210 	PINGROUP(86, EAST, qup5, _, _, _, _, _, _, _, _, _),
1211 	PINGROUP(87, EAST, qup5, _, _, _, _, _, _, _, _, _),
1212 	PINGROUP(88, EAST, qup5, _, _, _, _, _, _, _, _, _),
1213 	PINGROUP(89, SOUTH, tsif1_clk, qup4, qspi_cs, tgu_ch3, phase_flag, _, _, _, _, _),
1214 	PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, qspi_cs, mdp_vsync1,
1215 			    mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),
1216 	PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, qspi_data, tgu_ch1, _, qdss_cti, _, _, _),
1217 	PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, qspi_data, vfr_1, tgu_ch2, _, _, _, _),
1218 	PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, qspi_data, _, qdss, _, _, _, _),
1219 	PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, qspi_data, _, _, _, _, _, _),
1220 	PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, qspi_clk, _, _, _, _, _, _),
1221 	PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _, _),
1222 	PINGROUP(97, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _, _),
1223 	PINGROUP(98, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _, _),
1224 	PINGROUP(99, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
1225 	PINGROUP(100, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
1226 	PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _, _),
1227 	PINGROUP(102, NORTH, pci_e1, prng_rosc, _, _, _, _, _, _, _, _),
1228 	PINGROUP(103, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _, _),
1229 	PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _, _),
1230 	PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _, _),
1231 	PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _, _),
1232 	PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _, _),
1233 	PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _, _),
1234 	PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _, _),
1235 	PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _, _),
1236 	PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _, _),
1237 	PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _, _),
1238 	PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _, _),
1239 	PINGROUP(114, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
1240 	PINGROUP(115, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
1241 	PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _, _),
1242 	PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1243 	PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _, _),
1244 	PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1245 	PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1246 	PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1247 	PINGROUP(122, EAST, _, qdss, _, _, _, _, _, _, _, _),
1248 	PINGROUP(123, EAST, qup_l4, _, qdss, _, _, _, _, _, _, _),
1249 	PINGROUP(124, EAST, qup_l5, _, qdss, _, _, _, _, _, _, _),
1250 	PINGROUP(125, EAST, qup_l6, _, _, _, _, _, _, _, _, _),
1251 	PINGROUP(126, EAST, _, _, _, _, _, _, _, _, _, _),
1252 	PINGROUP(127, NORTH, _, _, _, _, _, _, _, _, _, _),
1253 	PINGROUP(128, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
1254 	PINGROUP(129, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
1255 	PINGROUP(130, NORTH, qlink_request, _, _, _, _, _, _, _, _, _),
1256 	PINGROUP(131, NORTH, qlink_enable, _, _, _, _, _, _, _, _, _),
1257 	PINGROUP(132, NORTH, _, _, _, _, _, _, _, _, _, _),
1258 	PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _, _),
1259 	PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _, _),
1260 	PINGROUP(135, NORTH, _, pa_indicator, _, _, _, _, _, _, _, _),
1261 	PINGROUP(136, NORTH, _, _, _, _, _, _, _, _, _, _),
1262 	PINGROUP(137, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1263 	PINGROUP(138, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1264 	PINGROUP(139, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1265 	PINGROUP(140, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1266 	PINGROUP(141, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1267 	PINGROUP(142, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1268 	PINGROUP(143, NORTH, _, nav_pps, nav_pps, _, phase_flag, _, _, _, _, _),
1269 	PINGROUP(144, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
1270 	PINGROUP(145, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
1271 	PINGROUP(146, NORTH, _, _, _, _, _, _, _, _, _, _),
1272 	PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _),
1273 	PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _),
1274 	PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _),
1275 	UFS_RESET(ufs_reset, 0x99f000),
1276 	SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6),
1277 	SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3),
1278 	SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0),
1279 };
1280 
1281 static const int sdm845_acpi_reserved_gpios[] = {
1282 	0, 1, 2, 3, 81, 82, 83, 84, -1
1283 };
1284 
1285 static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
1286 	.pins = sdm845_pins,
1287 	.npins = ARRAY_SIZE(sdm845_pins),
1288 	.functions = sdm845_functions,
1289 	.nfunctions = ARRAY_SIZE(sdm845_functions),
1290 	.groups = sdm845_groups,
1291 	.ngroups = ARRAY_SIZE(sdm845_groups),
1292 	.ngpios = 151,
1293 };
1294 
1295 static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = {
1296 	.pins = sdm845_pins,
1297 	.npins = ARRAY_SIZE(sdm845_pins),
1298 	.groups = sdm845_groups,
1299 	.ngroups = ARRAY_SIZE(sdm845_groups),
1300 	.reserved_gpios = sdm845_acpi_reserved_gpios,
1301 	.ngpios = 150,
1302 };
1303 
sdm845_pinctrl_probe(struct platform_device * pdev)1304 static int sdm845_pinctrl_probe(struct platform_device *pdev)
1305 {
1306 	int ret;
1307 
1308 	if (pdev->dev.of_node) {
1309 		ret = msm_pinctrl_probe(pdev, &sdm845_pinctrl);
1310 	} else if (has_acpi_companion(&pdev->dev)) {
1311 		ret = msm_pinctrl_probe(pdev, &sdm845_acpi_pinctrl);
1312 	} else {
1313 		dev_err(&pdev->dev, "DT and ACPI disabled\n");
1314 		return -EINVAL;
1315 	}
1316 
1317 	return ret;
1318 }
1319 
1320 #ifdef CONFIG_ACPI
1321 static const struct acpi_device_id sdm845_pinctrl_acpi_match[] = {
1322 	{ "QCOM0217"},
1323 	{ },
1324 };
1325 MODULE_DEVICE_TABLE(acpi, sdm845_pinctrl_acpi_match);
1326 #endif
1327 
1328 static const struct of_device_id sdm845_pinctrl_of_match[] = {
1329 	{ .compatible = "qcom,sdm845-pinctrl", },
1330 	{ },
1331 };
1332 
1333 static struct platform_driver sdm845_pinctrl_driver = {
1334 	.driver = {
1335 		.name = "sdm845-pinctrl",
1336 		.pm = &msm_pinctrl_dev_pm_ops,
1337 		.of_match_table = sdm845_pinctrl_of_match,
1338 		.acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match),
1339 	},
1340 	.probe = sdm845_pinctrl_probe,
1341 	.remove = msm_pinctrl_remove,
1342 };
1343 
sdm845_pinctrl_init(void)1344 static int __init sdm845_pinctrl_init(void)
1345 {
1346 	return platform_driver_register(&sdm845_pinctrl_driver);
1347 }
1348 arch_initcall(sdm845_pinctrl_init);
1349 
sdm845_pinctrl_exit(void)1350 static void __exit sdm845_pinctrl_exit(void)
1351 {
1352 	platform_driver_unregister(&sdm845_pinctrl_driver);
1353 }
1354 module_exit(sdm845_pinctrl_exit);
1355 
1356 MODULE_DESCRIPTION("QTI sdm845 pinctrl driver");
1357 MODULE_LICENSE("GPL v2");
1358 MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match);
1359