| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | smu7_hwmgr.c | 633 &data->dpm_table.sclk_table, in smu7_reset_dpm_tables()
691 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v0()
694 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
696 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
698 …data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
699 data->dpm_table.sclk_table.count++; in smu7_setup_dpm_tables_v0()
785 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v1()
787 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
790 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v1()
793 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
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| D | process_pptables_v1_0.c | 417 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; in get_sclk_voltage_dependency_table() local
431 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
433 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
436 sclk_table->count = (uint32_t)tonga_table->ucNumEntries; in get_sclk_voltage_dependency_table()
444 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
463 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
465 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
468 sclk_table->count = (uint32_t)polaris_table->ucNumEntries; in get_sclk_voltage_dependency_table()
476 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
486 *pp_tonga_sclk_dep_table = sclk_table; in get_sclk_voltage_dependency_table()
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| D | smu7_hwmgr.h | 104 struct smu7_single_dpm_table sclk_table; member
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| D | vega10_hwmgr.c | 3290 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_find_dpm_states_clocks_in_dpm_table() local
3298 for (i = 0; i < sclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3299 if (sclk == sclk_table->dpm_levels[i].value) in vega10_find_dpm_states_clocks_in_dpm_table()
3303 if (i >= sclk_table->count) { in vega10_find_dpm_states_clocks_in_dpm_table()
3304 if (sclk > sclk_table->dpm_levels[i-1].value) { in vega10_find_dpm_states_clocks_in_dpm_table()
3306 sclk_table->dpm_levels[i-1].value = sclk; in vega10_find_dpm_states_clocks_in_dpm_table()
4471 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_print_clock_levels() local
4488 for (i = 0; i < sclk_table->count; i++) in vega10_print_clock_levels()
4490 i, sclk_table->dpm_levels[i].value / 100, in vega10_print_clock_levels()
4751 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_get_sclk_od() local
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| D | smu8_hwmgr.c | 1516 struct phm_clock_voltage_dependency_table *sclk_table = in smu8_print_clock_levels() local
1528 for (i = 0; i < sclk_table->count; i++) in smu8_print_clock_levels()
1530 i, sclk_table->entries[i].clk / 100, in smu8_print_clock_levels()
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| D | vega12_hwmgr.c | 2511 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2514 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
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| D | vega20_hwmgr.c | 1442 struct vega20_single_dpm_table *sclk_table = in vega20_get_sclk_od() local
1446 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; in vega20_get_sclk_od()
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| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | vegam_smumgr.c | 885 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
888 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
906 (uint8_t)dpm_table->sclk_table.count; in vegam_populate_all_graphic_levels()
908 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in vegam_populate_all_graphic_levels()
910 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
919 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
944 for (i = 2; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
1296 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in vegam_program_memory_timing_parameters()
1299 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1383 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in vegam_populate_smc_boot_level()
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| D | polaris10_smumgr.c | 1001 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1004 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1019 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels()
1021 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in polaris10_populate_all_graphic_levels()
1029 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1054 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1370 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters()
1373 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
1459 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in polaris10_populate_smc_boot_level()
1519 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = in polaris10_populate_clock_stretcher_data_table() local
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| D | fiji_smumgr.c | 1026 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels()
1028 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1042 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
1046 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels()
1048 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in fiji_populate_all_graphic_levels()
1055 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1080 for (i = 2; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1320 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1537 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters()
1540 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
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| D | tonga_smumgr.c | 710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
726 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels()
727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
731 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels()
733 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in tonga_populate_all_graphic_levels()
740 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
770 for (i = 2; i < dpm_table->sclk_table.count; i++) in tonga_populate_all_graphic_levels()
1497 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters()
1500 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
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| D | iceland_smumgr.c | 980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1001 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels()
1003 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in iceland_populate_all_graphic_levels()
1026 for (i = 2; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
1621 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters()
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1657 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in iceland_populate_smc_boot_level()
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| D | ci_smumgr.c | 484 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
486 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
492 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
499 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
501 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
1658 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in ci_program_memory_timing_parameters()
1661 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1694 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in ci_populate_smc_boot_level()
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| /Linux-v5.4/drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 2555 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2558 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
3289 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3291 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3298 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3304 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3306 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3464 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3479 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3482 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
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| D | ci_dpm.h | 69 struct ci_single_dpm_table sclk_table; member
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