| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/ |
| D | navi10_ppt.c | 1211 uint32_t *sclk_mask, in navi10_get_profiling_clk_mask() argument
1219 if (sclk_mask) in navi10_get_profiling_clk_mask()
1220 *sclk_mask = 0; in navi10_get_profiling_clk_mask()
1225 if(sclk_mask) { in navi10_get_profiling_clk_mask()
1229 *sclk_mask = level_count - 1; in navi10_get_profiling_clk_mask()
|
| D | arcturus_ppt.c | 1288 uint32_t *sclk_mask, in arcturus_get_profiling_clk_mask() argument
1305 *sclk_mask = 0; in arcturus_get_profiling_clk_mask()
1312 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL; in arcturus_get_profiling_clk_mask()
1318 *sclk_mask = 0; in arcturus_get_profiling_clk_mask()
1322 *sclk_mask = gfx_dpm_table->count - 1; in arcturus_get_profiling_clk_mask()
|
| D | amdgpu_smu.c | 1568 uint32_t sclk_mask, mclk_mask, soc_mask; in smu_default_set_performance_level() local
1585 &sclk_mask, in smu_default_set_performance_level()
1590 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); in smu_default_set_performance_level()
|
| D | vega20_ppt.c | 1985 uint32_t *sclk_mask, in vega20_get_profiling_clk_mask() argument
2001 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2008 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL; in vega20_get_profiling_clk_mask()
2014 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2018 *sclk_mask = gfx_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
|
| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 1583 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1590 *sclk_mask = 0; in vega12_get_profiling_clk_mask()
1597 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; in vega12_get_profiling_clk_mask()
1603 *sclk_mask = 0; in vega12_get_profiling_clk_mask()
1607 *sclk_mask = gfx_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1637 uint32_t sclk_mask = 0; in vega12_dpm_force_dpm_level() local
1655 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1658 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); in vega12_dpm_force_dpm_level()
|
| D | smu7_hwmgr.c | 2728 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
2759 *sclk_mask = count; in smu7_get_profiling_clk()
2764 *sclk_mask = 0; in smu7_get_profiling_clk()
2769 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
2777 *sclk_mask = count; in smu7_get_profiling_clk()
2782 *sclk_mask = 0; in smu7_get_profiling_clk()
2787 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; in smu7_get_profiling_clk()
2806 uint32_t sclk_mask = 0; in smu7_force_dpm_level() local
2811 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
2827 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
[all …]
|
| D | vega20_hwmgr.c | 2474 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2481 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2488 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL; in vega20_get_profiling_clk_mask()
2494 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2498 *sclk_mask = gfx_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2673 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2692 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2695 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); in vega20_dpm_force_dpm_level()
|
| D | vega10_hwmgr.c | 4032 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4040 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; in vega10_get_profiling_clk_mask()
4048 *sclk_mask = 0; in vega10_get_profiling_clk_mask()
4052 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; in vega10_get_profiling_clk_mask()
4141 uint32_t sclk_mask = 0; in vega10_dpm_force_dpm_level() local
4146 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4162 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4165 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); in vega10_dpm_force_dpm_level()
|
| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/inc/ |
| D | amdgpu_smu.h | 441 uint32_t *sclk_mask,
673 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \ argument
674 …ng_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (…
|
