Searched refs:sclk_cntl (Results 1 – 4 of 4) sorted by relevance
963 union sclk_cntl_u sclk_cntl; member1159 w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL; in w100_pll_set_clk()1160 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); in w100_pll_set_clk()1208 w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL; in w100_pwm_setup()1209 w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = 0x0; /* Pfast = 1 */ in w100_pwm_setup()1210 w100_pwr_state.sclk_cntl.f.sclk_clkon_hys = 0x3; in w100_pwm_setup()1211 w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = 0x0; /* Pslow = 1 */ in w100_pwm_setup()1212 w100_pwr_state.sclk_cntl.f.disp_cg_ok2switch_en = 0x0; in w100_pwm_setup()1213 w100_pwr_state.sclk_cntl.f.sclk_force_reg = 0x0; /* Dynamic */ in w100_pwm_setup()1214 w100_pwr_state.sclk_cntl.f.sclk_force_disp = 0x0; /* Dynamic */ in w100_pwm_setup()[all …]
200 u32 sclk_cntl; in r420_clock_resume() local204 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); in r420_clock_resume()205 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); in r420_clock_resume()207 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); in r420_clock_resume()208 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); in r420_clock_resume()
356 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; in r100_pm_misc() local380 sclk_cntl = RREG32_PLL(SCLK_CNTL); in r100_pm_misc()422 sclk_cntl &= ~FORCE_HDP; in r100_pm_misc()424 sclk_cntl |= FORCE_HDP; in r100_pm_misc()426 WREG32_PLL(SCLK_CNTL, sclk_cntl); in r100_pm_misc()
825 u32 sclk_cntl, mclk_cntl, sclk_more_cntl; in radeon_pm_setup_for_suspend() local837 sclk_cntl = INPLL( pllSCLK_CNTL); in radeon_pm_setup_for_suspend()838 sclk_cntl |= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT| in radeon_pm_setup_for_suspend()864 sclk_cntl |= SCLK_CNTL__FORCE_RE; in radeon_pm_setup_for_suspend()866 sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT | in radeon_pm_setup_for_suspend()872 OUTPLL( pllSCLK_CNTL, sclk_cntl); in radeon_pm_setup_for_suspend()
