Searched refs:rt_sysc_r32 (Results 1 – 15 of 15) sorted by relevance
312 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()313 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); in rt3883_pci_preinit()314 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()325 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()329 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()333 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()337 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()387 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()394 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()398 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
242 if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) { in mt7620_pci_hw_init()
125 if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0) in ralink_clk_init()130 clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); in ralink_clk_init()137 fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; in ralink_clk_init()138 syscfg = rt_sysc_r32(SYSC_REG_SYSCFG); in ralink_clk_init()
33 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); in ralink_assert_device()48 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); in ralink_deassert_device()
386 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); in mt7620_get_xtal_rate()398 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); in mt7620_get_periph_rate()414 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); in mt7620_get_cpu_pll_rate()440 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); in mt7620_get_pll_rate()457 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in mt7620_get_cpu_rate()490 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in mt7620_get_sys_rate()578 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in ralink_clk_init()
135 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); in ralink_clk_init()188 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); in ralink_clk_init()
43 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); in ralink_clk_init()
70 syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0); in ralink_clk_init()
40 static inline u32 rt_sysc_r32(unsigned reg) in rt_sysc_r32() function47 u32 val = rt_sysc_r32(reg) & ~clr; in rt_sysc_m32()
135 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; in mt7620_get_eco()
100 if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) in mt7621_wdt_bootcause()
114 if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) in rt288x_wdt_bootcause()
232 u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID); in mt7621_control_assert()242 u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID); in mt7621_control_deassert()
140 u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); in mt7621_set_phy_for_ssc()
141 mode = rt_sysc_r32(reg); in rt2880_pmx_group_enable()
