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Searched refs:reg_off (Results 1 – 25 of 46) sorted by relevance

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/Linux-v5.4/drivers/mmc/host/
Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
[all …]
/Linux-v5.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_vbif.c59 u32 reg_off; in dpu_hw_set_mem_type() local
74 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1; in dpu_hw_set_mem_type()
76 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0; in dpu_hw_set_mem_type()
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
90 u32 reg_off; in dpu_hw_set_limit_conf() local
94 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_set_limit_conf()
96 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_set_limit_conf()
98 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf()
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
[all …]
Ddpu_hw_catalog.c70 .reg_off = 0x2AC, .bit_off = 0},
72 .reg_off = 0x2B4, .bit_off = 0},
74 .reg_off = 0x2BC, .bit_off = 0},
76 .reg_off = 0x2C4, .bit_off = 0},
78 .reg_off = 0x2AC, .bit_off = 8},
80 .reg_off = 0x2B4, .bit_off = 8},
82 .reg_off = 0x2BC, .bit_off = 8},
84 .reg_off = 0x2C4, .bit_off = 8},
Ddpu_hw_top.c96 u32 reg_off, bit_off; in dpu_hw_setup_clk_force_ctrl() local
108 reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; in dpu_hw_setup_clk_force_ctrl()
111 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_setup_clk_force_ctrl()
118 DPU_REG_WRITE(c, reg_off, new_val); in dpu_hw_setup_clk_force_ctrl()
Ddpu_hw_util.c63 u32 reg_off, in dpu_reg_write() argument
70 name, c->blk_off + reg_off, val); in dpu_reg_write()
71 writel_relaxed(val, c->base_off + c->blk_off + reg_off); in dpu_reg_write()
74 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off) in dpu_reg_read() argument
76 return readl_relaxed(c->base_off + c->blk_off + reg_off); in dpu_reg_read()
Ddpu_hw_util.h301 u32 reg_off,
304 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
/Linux-v5.4/drivers/pinctrl/
Dpinctrl-digicolor.c129 int bit_off, reg_off; in dc_set_mux() local
132 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
134 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
137 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
147 int bit_off, reg_off; in dc_pmx_request_gpio() local
150 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
152 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
170 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
176 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
178 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
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/Linux-v5.4/drivers/clk/meson/
Daxg.c28 .reg_off = HHI_MPLL_CNTL,
33 .reg_off = HHI_MPLL_CNTL,
38 .reg_off = HHI_MPLL_CNTL,
43 .reg_off = HHI_MPLL_CNTL2,
48 .reg_off = HHI_MPLL_CNTL,
53 .reg_off = HHI_MPLL_CNTL,
92 .reg_off = HHI_SYS_PLL_CNTL,
97 .reg_off = HHI_SYS_PLL_CNTL,
102 .reg_off = HHI_SYS_PLL_CNTL,
107 .reg_off = HHI_SYS_PLL_CNTL,
[all …]
Dg12a-aoclk.c121 .reg_off = AO_RTC_ALT_CLK_CNTL0,
126 .reg_off = AO_RTC_ALT_CLK_CNTL0,
131 .reg_off = AO_RTC_ALT_CLK_CNTL1,
136 .reg_off = AO_RTC_ALT_CLK_CNTL1,
141 .reg_off = AO_RTC_ALT_CLK_CNTL0,
212 .reg_off = AO_CEC_CLK_CNTL_REG0,
217 .reg_off = AO_CEC_CLK_CNTL_REG0,
222 .reg_off = AO_CEC_CLK_CNTL_REG1,
227 .reg_off = AO_CEC_CLK_CNTL_REG1,
232 .reg_off = AO_CEC_CLK_CNTL_REG0,
Dparm.h25 u16 reg_off; member
34 regmap_read(map, p->reg_off, &val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
Dgxbb.c88 .reg_off = HHI_MPLL_CNTL,
93 .reg_off = HHI_MPLL_CNTL,
98 .reg_off = HHI_MPLL_CNTL,
103 .reg_off = HHI_MPLL_CNTL2,
108 .reg_off = HHI_MPLL_CNTL,
113 .reg_off = HHI_MPLL_CNTL,
165 .reg_off = HHI_HDMI_PLL_CNTL,
170 .reg_off = HHI_HDMI_PLL_CNTL,
175 .reg_off = HHI_HDMI_PLL_CNTL,
180 .reg_off = HHI_HDMI_PLL_CNTL2,
[all …]
Dg12a.c32 .reg_off = HHI_FIX_PLL_CNTL0,
37 .reg_off = HHI_FIX_PLL_CNTL0,
42 .reg_off = HHI_FIX_PLL_CNTL0,
47 .reg_off = HHI_FIX_PLL_CNTL1,
52 .reg_off = HHI_FIX_PLL_CNTL0,
57 .reg_off = HHI_FIX_PLL_CNTL0,
101 .reg_off = HHI_SYS_PLL_CNTL0,
106 .reg_off = HHI_SYS_PLL_CNTL0,
111 .reg_off = HHI_SYS_PLL_CNTL0,
116 .reg_off = HHI_SYS_PLL_CNTL0,
[all …]
Dgxbb-aoclk.c88 .reg_off = AO_RTC_ALT_CLK_CNTL0,
93 .reg_off = AO_RTC_ALT_CLK_CNTL0,
98 .reg_off = AO_RTC_ALT_CLK_CNTL1,
103 .reg_off = AO_RTC_ALT_CLK_CNTL1,
108 .reg_off = AO_RTC_ALT_CLK_CNTL0,
Daxg-aoclk.c102 .reg_off = AO_RTC_ALT_CLK_CNTL0,
107 .reg_off = AO_RTC_ALT_CLK_CNTL0,
112 .reg_off = AO_RTC_ALT_CLK_CNTL1,
117 .reg_off = AO_RTC_ALT_CLK_CNTL1,
122 .reg_off = AO_RTC_ALT_CLK_CNTL0,
Dmeson8b.c67 .reg_off = HHI_MPLL_CNTL,
72 .reg_off = HHI_MPLL_CNTL,
77 .reg_off = HHI_MPLL_CNTL,
82 .reg_off = HHI_MPLL_CNTL2,
87 .reg_off = HHI_MPLL_CNTL,
92 .reg_off = HHI_MPLL_CNTL,
131 .reg_off = HHI_VID_PLL_CNTL,
136 .reg_off = HHI_VID_PLL_CNTL,
141 .reg_off = HHI_VID_PLL_CNTL,
146 .reg_off = HHI_VID_PLL_CNTL2,
[all …]
/Linux-v5.4/drivers/irqchip/
Dirq-davinci-aintc.c82 unsigned int irq_off, reg_off, prio, shift; in davinci_aintc_init() local
125 for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG; in davinci_aintc_init()
126 reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) { in davinci_aintc_init()
129 davinci_aintc_writel(prio, reg_off); in davinci_aintc_init()
156 for (irq_off = 0, reg_off = 0; in davinci_aintc_init()
158 irq_off += 32, reg_off += 0x04) in davinci_aintc_init()
159 davinci_aintc_setup_gc(davinci_aintc_base + reg_off, in davinci_aintc_init()
/Linux-v5.4/drivers/pinctrl/spear/
Dpinctrl-plgpio.c83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in is_plgpio_set() local
84 u32 val = readl_relaxed(reg_off); in is_plgpio_set()
92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_set() local
93 u32 val = readl_relaxed(reg_off); in plgpio_reg_set()
95 writel_relaxed(val | (1 << offset), reg_off); in plgpio_reg_set()
101 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_reset() local
102 u32 val = readl_relaxed(reg_off); in plgpio_reg_reset()
104 writel_relaxed(val & ~(1 << offset), reg_off); in plgpio_reg_reset()
323 void __iomem *reg_off; in plgpio_irq_set_type() local
340 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); in plgpio_irq_set_type()
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/Linux-v5.4/drivers/thermal/samsung/
Dexynos_tmu.c449 unsigned int reg_off, j; in exynos5433_tmu_set_trip_temp() local
453 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; in exynos5433_tmu_set_trip_temp()
456 reg_off = EXYNOS5433_THD_TEMP_RISE3_0; in exynos5433_tmu_set_trip_temp()
460 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_temp()
463 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_temp()
469 unsigned int reg_off, j; in exynos5433_tmu_set_trip_hyst() local
473 reg_off = EXYNOS5433_THD_TEMP_FALL7_4; in exynos5433_tmu_set_trip_hyst()
476 reg_off = EXYNOS5433_THD_TEMP_FALL3_0; in exynos5433_tmu_set_trip_hyst()
480 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_hyst()
483 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_hyst()
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/Linux-v5.4/drivers/net/ethernet/cavium/liquidio/
Docteon_device.h752 #define octeon_write_csr(oct_dev, reg_off, value) \ argument
753 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
755 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument
756 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
758 #define octeon_read_csr(oct_dev, reg_off) \ argument
759 readl((oct_dev)->mmio[0].hw_addr + (reg_off))
761 #define octeon_read_csr64(oct_dev, reg_off) \ argument
762 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
/Linux-v5.4/drivers/misc/habanalabs/goya/
Dgoya.c770 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); in goya_init_dma_qman() local
782 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); in goya_init_dma_qman()
783 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); in goya_init_dma_qman()
785 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); in goya_init_dma_qman()
786 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
787 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
789 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); in goya_init_dma_qman()
790 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); in goya_init_dma_qman()
791 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); in goya_init_dma_qman()
792 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); in goya_init_dma_qman()
[all …]
/Linux-v5.4/sound/soc/xilinx/
Dxlnx_i2s.c42 u32 reg_off, chan_id; in xlnx_i2s_hw_params() local
48 reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4); in xlnx_i2s_hw_params()
49 writel(chan_id, base + reg_off); in xlnx_i2s_hw_params()
/Linux-v5.4/drivers/staging/vt6656/
Dusbpipe.c71 int vnt_control_out_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 data) in vnt_control_out_u8() argument
74 reg_off, reg, sizeof(u8), &data); in vnt_control_out_u8()
115 int vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data) in vnt_control_in_u8() argument
118 reg_off, reg, sizeof(u8), data); in vnt_control_in_u8()
/Linux-v5.4/drivers/mtd/nand/raw/
Dqcom_nandc.c807 int reg_off, const void *vaddr, in prep_bam_dma_desc_cmd() argument
821 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
827 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
893 int reg_off, const void *vaddr, int size, in prep_adm_dma_desc() argument
930 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
934 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
1046 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
1052 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
1064 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
1070 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
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/Linux-v5.4/arch/x86/kvm/
Dlapic.h152 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) in kvm_lapic_get_reg() argument
154 return *((u32 *) (apic->regs + reg_off)); in kvm_lapic_get_reg()
157 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) in kvm_lapic_set_reg() argument
159 *((u32 *) (apic->regs + reg_off)) = val; in kvm_lapic_set_reg()
/Linux-v5.4/drivers/clk/
Dclk-stm32mp1.c329 u32 reg_off; member
340 u32 reg_off; member
348 u32 reg_off; member
391 gate_cfg->reg_off + base, in _clk_hw_register_gate()
422 div_cfg->reg_off + base, in _clk_hw_register_divider_table()
440 mux_cfg->reg_off + base, mux_cfg->shift, in _clk_hw_register_mux()
485 mmux->mux.reg = cfg->mux->reg_off + base; in _get_stm32_mux()
500 mux->reg = cfg->mux->reg_off + base; in _get_stm32_mux()
523 div->reg = cfg->div->reg_off + base; in _get_stm32_div()
546 mgate->gate.reg = cfg->gate->reg_off + base; in _get_stm32_gate()
[all …]

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