| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 39 #define REG_READ(reg_name) \ argument
40 dm_read_reg(CTX, REG(reg_name))
42 #define REG_WRITE(reg_name, value) \ argument
43 dm_write_reg(CTX, REG(reg_name), value)
54 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
56 REG(reg_name), \
60 #define FN(reg_name, field) \ argument
61 FD(reg_name##__##field)
63 #define REG_SET(reg_name, initial_val, field, val) \ argument
64 REG_SET_N(reg_name, 1, initial_val, \
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| D | hw_factory_dcn21.c | 58 #define REG(reg_name)\ argument
59 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
61 #define SF_HPD(reg_name, field_name, post_fix)\ argument
62 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
64 #define REGI(reg_name, block, id)\ argument
65 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
66 mm ## block ## id ## _ ## reg_name
68 #define SF(reg_name, field_name, post_fix)\ argument
69 .field_name = reg_name ## __ ## field_name ## post_fix
100 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| D | hw_translate_dcn21.c | 56 #define REG(reg_name)\ argument
57 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
58 #define SF_HPD(reg_name, field_name, post_fix)\ argument
59 .field_name = reg_name ## __ ## field_name ## post_fix
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| D | hw_factory_dcn20.c | 60 #define REG(reg_name)\ argument
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define SF_HPD(reg_name, field_name, post_fix)\ argument
64 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
66 #define REGI(reg_name, block, id)\ argument
67 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
68 mm ## block ## id ## _ ## reg_name
70 #define SF(reg_name, field_name, post_fix)\ argument
71 .field_name = reg_name ## __ ## field_name ## post_fix
103 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| D | hw_translate_dcn20.c | 56 #define REG(reg_name)\ argument
57 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
58 #define SF_HPD(reg_name, field_name, post_fix)\ argument
59 .field_name = reg_name ## __ ## field_name ## post_fix
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| D | hw_factory_dce120.c | 46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
60 #define REG(reg_name)\ argument
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| D | hw_translate_dce120.c | 51 #define REG(reg_name)\ argument
52 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
54 #define REGI(reg_name, block, id)\ argument
55 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
56 mm ## block ## id ## _ ## reg_name
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/ |
| D | dm_services.h | 111 #define get_reg_field_value(reg_value, reg_name, reg_field)\ argument
114 reg_name ## __ ## reg_field ## _MASK,\
115 reg_name ## __ ## reg_field ## __SHIFT)
127 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ argument
131 reg_name ## __ ## reg_field ## _MASK,\
132 reg_name ## __ ## reg_field ## __SHIFT)
165 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
166 …generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name +…
169 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
170 …generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + ins…
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| D | hw_factory_dcn10.c | 47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define REGI(reg_name, block, id)\ argument
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
62 mm ## block ## id ## _ ## reg_name
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## __ ## field_name ## post_fix
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| D | hw_translate_dcn10.c | 51 #define REG(reg_name)\ argument
52 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
54 #define REGI(reg_name, block, id)\ argument
55 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
56 mm ## block ## id ## _ ## reg_name
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| /Linux-v5.4/drivers/crypto/ux500/cryp/ |
| D | cryp_p.h | 23 #define CRYP_SET_BITS(reg_name, mask) \ argument
24 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
26 #define CRYP_WRITE_BIT(reg_name, val, mask) \ argument
27 writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
28 ((val) & (mask))), reg_name)
30 #define CRYP_TEST_BITS(reg_name, val) \ argument
31 (readl_relaxed(reg_name) & (val))
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| D | hw_factory_dce110.c | 42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = reg_name ## __ ## field_name ## post_fix
45 #define REG(reg_name)\ argument
46 mm ## reg_name
48 #define REGI(reg_name, block, id)\ argument
49 mm ## block ## id ## _ ## reg_name
83 #define SF_DDC(reg_name, field_name, post_fix)\ argument
84 .field_name = reg_name ## __ ## field_name ## post_fix
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dwb.h | 36 #define SR(reg_name)\ argument
37 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
38 mm ## reg_name
40 #define SRI(reg_name, block, id)\ argument
41 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
42 mm ## block ## id ## _ ## reg_name
45 #define SRII(reg_name, block, id)\ argument
46 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
47 mm ## block ## id ## _ ## reg_name
49 #define SF(reg_name, field_name, post_fix)\ argument
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_vmid.h | 37 #define SRI(reg_name, block, id)\ argument
38 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
39 mm ## block ## id ## _ ## reg_name
41 #define SF(reg_name, field_name, post_fix)\ argument
42 .field_name = reg_name ## __ ## field_name ## post_fix
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| D | dcn20_dwb.h | 37 #define SR(reg_name)\ argument
38 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
39 mm ## reg_name
41 #define SRI(reg_name, block, id)\ argument
42 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
43 mm ## block ## id ## _ ## reg_name
45 #define SRI2(reg_name, block, id)\ argument
46 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
47 mm ## reg_name
49 #define SRII(reg_name, block, id)\ argument
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| D | dcn20_mmhubbub.h | 39 #define SR(reg_name)\ argument
40 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
41 mm ## reg_name
43 #define SRI(reg_name, block, id)\ argument
44 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## id ## _ ## reg_name
47 #define SRI2(reg_name, block, id)\ argument
48 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
49 mm ## reg_name
51 #define SRII(reg_name, block, id)\ argument
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| D | dcn20_dccg.h | 44 #define DCCG_SF(reg_name, field_name, post_fix)\ argument
45 .field_name = reg_name ## __ ## field_name ## post_fix
47 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ argument
48 ….field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name…
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr_clk.c | 43 #define CLK_REG(reg_name, block, inst)\ argument
44 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## _ ## inst ## _ ## reg_name
47 #define REG(reg_name) \ argument
48 CLK_REG(reg_name, CLK0, 0)
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| D | rv1_clk_mgr_vbios_smu.c | 62 #define REG(reg_name) \ argument
63 (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
65 #define FN(reg_name, field) \ argument
66 FD(reg_name##__##field)
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr_vbios_smu.c | 35 #define REG(reg_name) \ argument
36 (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
38 #define FN(reg_name, field) \ argument
39 FD(reg_name##__##field)
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr_internal.h | 83 #define CLK_SRI(reg_name, block, inst)\ argument
84 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
85 mm ## block ## _ ## inst ## _ ## reg_name
106 #define CLK_SF(reg_name, field_name, post_fix)\ argument
107 .field_name = reg_name ## __ ## field_name ## post_fix
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| /Linux-v5.4/drivers/crypto/ux500/hash/ |
| D | hash_alg.h | 98 #define HASH_SET_BITS(reg_name, mask) \ argument
99 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
101 #define HASH_CLEAR_BITS(reg_name, mask) \ argument
102 writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| D | dce112_clk_mgr.c | 37 #define SR(reg_name)\ argument
38 .reg_name = mm ## reg_name
41 #define SRI(reg_name, block, id)\ argument
42 .reg_name = mm ## block ## id ## _ ## reg_name
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
| D | hw_factory_dce80.c | 41 #define REG(reg_name)\ argument
42 mm ## reg_name
83 #define SF_DDC(reg_name, field_name, post_fix)\ argument
84 .field_name = reg_name ## __ ## field_name ## post_fix
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 285 #define SR(reg_name)\ argument
286 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
287 mm ## reg_name
289 #define SRI(reg_name, block, id)\ argument
290 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
291 mm ## block ## id ## _ ## reg_name
293 #define SRIR(var_name, reg_name, block, id)\ argument
294 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
295 mm ## block ## id ## _ ## reg_name
297 #define SRII(reg_name, block, id)\ argument
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