Searched refs:reference_divider (Results 1 – 13 of 13) sorted by relevance
52 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local61 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()69 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()96 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_sclk_value()131 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local139 reference_divider = dividers.ref_div + 1; in rv730_populate_mclk_value()172 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_mclk_value()
132 u32 reference_divider; in rv740_populate_sclk_value() local141 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()143 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()164 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv740_populate_sclk_value()
324 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local333 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()336 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()501 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local510 reference_divider = 1 + dividers.ref_div; in rv770_populate_sclk_value()517 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()543 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv770_populate_sclk_value()
2013 u32 reference_divider; in ni_calculate_sclk_params() local2022 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()2046 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ni_calculate_sclk_params()
4797 u32 reference_divider; in si_calculate_sclk_params() local4806 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()4808 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()4829 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()
3170 u32 reference_divider; in ci_calculate_sclk_params() local3180 reference_divider = 1 + dividers.ref_div; in ci_calculate_sclk_params()3193 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ci_calculate_sclk_params()
237 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance()337 if (pll_settings->reference_divider) { in calculate_pixel_clock_pll_dividers()338 min_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()339 max_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()452 pll_settings->reference_divider = in pll_adjust_pix_clk()453 bp_adjust_pixel_clock_params.reference_divider; in pll_adjust_pix_clk()696 pll_settings->reference_divider * ss_data->modulation_freq_hz); in calculate_ss()865 bp_pc_params.reference_divider = pll_settings->reference_divider; in dce110_program_pix_clk()
200 uint32_t reference_divider; member217 uint32_t reference_divider; member
112 uint32_t reference_divider; member
957 cpu_to_le16((uint16_t)bp_params->reference_divider); in set_pixel_clock_v3()1028 (uint8_t)(bp_params->reference_divider); in set_pixel_clock_v5()1104 (uint8_t) bp_params->reference_divider; in set_pixel_clock_v6()1520 bp_params->reference_divider = params.sOutput.ucRefDiv; in adjust_display_pll_v3()
806 uint32_t reference_divider; in iceland_calculate_sclk_params() local819 reference_divider = 1 + dividers.uc_pll_ref_div; in iceland_calculate_sclk_params()849 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in iceland_calculate_sclk_params()
549 uint32_t reference_divider; in tonga_calculate_sclk_params() local562 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()592 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in tonga_calculate_sclk_params()
5259 u32 reference_divider; in si_calculate_sclk_params() local5268 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()5270 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()5291 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()
