| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v2_4.c | 280 u32 ref_and_mask = 0; in sdma_v2_4_ring_emit_hdp_flush() local
283 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
285 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v2_4_ring_emit_hdp_flush()
292 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v2_4_ring_emit_hdp_flush()
293 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v2_4_ring_emit_hdp_flush()
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| D | sdma_v3_0.c | 454 u32 ref_and_mask = 0; in sdma_v3_0_ring_emit_hdp_flush() local
457 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
459 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush()
466 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v3_0_ring_emit_hdp_flush()
467 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v3_0_ring_emit_hdp_flush()
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| D | cik_sdma.c | 251 u32 ref_and_mask; in cik_sdma_ring_emit_hdp_flush() local
254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; in cik_sdma_ring_emit_hdp_flush()
256 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; in cik_sdma_ring_emit_hdp_flush()
261 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
262 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_ring_emit_hdp_flush()
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| D | sdma_v5_0.c | 408 u32 ref_and_mask = 0; in sdma_v5_0_ring_emit_hdp_flush() local
412 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; in sdma_v5_0_ring_emit_hdp_flush()
414 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; in sdma_v5_0_ring_emit_hdp_flush()
421 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_0_ring_emit_hdp_flush()
422 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_0_ring_emit_hdp_flush()
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| D | sdma_v4_0.c | 749 u32 ref_and_mask = 0; in sdma_v4_0_ring_emit_hdp_flush() local
752 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v4_0_ring_emit_hdp_flush()
757 ref_and_mask, ref_and_mask, 10); in sdma_v4_0_ring_emit_hdp_flush()
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| D | gfx_v7_0.c | 2133 u32 ref_and_mask; in gfx_v7_0_ring_emit_hdp_flush() local
2139 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2142 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2148 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v7_0_ring_emit_hdp_flush()
2157 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2158 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
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| D | gfx_v10_0.c | 4386 u32 ref_and_mask, reg_mem_engine; in gfx_v10_0_ring_emit_hdp_flush() local
4392 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
4395 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
4402 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v10_0_ring_emit_hdp_flush()
4409 ref_and_mask, ref_and_mask, 0x20); in gfx_v10_0_ring_emit_hdp_flush()
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| D | gfx_v9_0.c | 4990 u32 ref_and_mask, reg_mem_engine; in gfx_v9_0_ring_emit_hdp_flush() local
4996 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
4999 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5006 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_0_ring_emit_hdp_flush()
5013 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_0_ring_emit_hdp_flush()
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| D | gfx_v8_0.c | 6073 u32 ref_and_mask, reg_mem_engine; in gfx_v8_0_ring_emit_hdp_flush() local
6079 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6082 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6089 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v8_0_ring_emit_hdp_flush()
6099 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
6100 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
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| /Linux-v5.4/drivers/gpu/drm/radeon/ |
| D | cik_sdma.c | 175 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
178 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
180 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
186 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
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| D | cik.c | 3512 u32 ref_and_mask; in cik_hdp_flush_cp_ring_emit() local
3520 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3523 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3530 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
3540 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3541 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
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