1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * aQuantia Corporation Network Driver 4 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 5 */ 6 7 /* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware 8 * abstraction layer. 9 */ 10 11 #ifndef HW_ATL_UTILS_H 12 #define HW_ATL_UTILS_H 13 14 #define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); } 15 16 /* Hardware tx descriptor */ 17 struct __packed hw_atl_txd_s { 18 u64 buf_addr; 19 u32 ctl; 20 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */ 21 }; 22 23 /* Hardware tx context descriptor */ 24 struct __packed hw_atl_txc_s { 25 u32 rsvd; 26 u32 len; 27 u32 ctl; 28 u32 len2; 29 }; 30 31 /* Hardware rx descriptor */ 32 struct __packed hw_atl_rxd_s { 33 u64 buf_addr; 34 u64 hdr_addr; 35 }; 36 37 /* Hardware rx descriptor writeback */ 38 struct __packed hw_atl_rxd_wb_s { 39 u32 type; 40 u32 rss_hash; 41 u16 status; 42 u16 pkt_len; 43 u16 next_desc_ptr; 44 u16 vlan; 45 }; 46 47 struct __packed hw_atl_stats_s { 48 u32 uprc; 49 u32 mprc; 50 u32 bprc; 51 u32 erpt; 52 u32 uptc; 53 u32 mptc; 54 u32 bptc; 55 u32 erpr; 56 u32 mbtc; 57 u32 bbtc; 58 u32 mbrc; 59 u32 bbrc; 60 u32 ubrc; 61 u32 ubtc; 62 u32 dpc; 63 }; 64 65 union __packed ip_addr { 66 struct { 67 u8 addr[16]; 68 } v6; 69 struct { 70 u8 padding[12]; 71 u8 addr[4]; 72 } v4; 73 }; 74 75 struct __packed hw_atl_utils_fw_rpc { 76 u32 msg_id; 77 78 union { 79 struct { 80 u32 pong; 81 } msg_ping; 82 83 struct { 84 u8 mac_addr[6]; 85 u32 ip_addr_cnt; 86 87 struct { 88 union ip_addr addr; 89 union ip_addr mask; 90 } ip[1]; 91 } msg_arp; 92 93 struct { 94 u32 len; 95 u8 packet[1514U]; 96 } msg_inject; 97 98 struct { 99 u32 priority; 100 u32 wol_packet_type; 101 u32 pattern_id; 102 u32 next_wol_pattern_offset; 103 104 union { 105 struct { 106 u32 flags; 107 u8 ipv4_source_address[4]; 108 u8 ipv4_dest_address[4]; 109 u16 tcp_source_port_number; 110 u16 tcp_dest_port_number; 111 } ipv4_tcp_syn_parameters; 112 113 struct { 114 u32 flags; 115 u8 ipv6_source_address[16]; 116 u8 ipv6_dest_address[16]; 117 u16 tcp_source_port_number; 118 u16 tcp_dest_port_number; 119 } ipv6_tcp_syn_parameters; 120 121 struct { 122 u32 flags; 123 } eapol_request_id_message_parameters; 124 125 struct { 126 u32 flags; 127 u32 mask_offset; 128 u32 mask_size; 129 u32 pattern_offset; 130 u32 pattern_size; 131 } wol_bit_map_pattern; 132 133 struct { 134 u8 mac_addr[ETH_ALEN]; 135 } wol_magic_packet_patter; 136 } wol_pattern; 137 } msg_wol; 138 139 struct { 140 union { 141 u32 pattern_mask; 142 143 struct { 144 u32 reason_arp_v4_pkt : 1; 145 u32 reason_ipv4_ping_pkt : 1; 146 u32 reason_ipv6_ns_pkt : 1; 147 u32 reason_ipv6_ping_pkt : 1; 148 u32 reason_link_up : 1; 149 u32 reason_link_down : 1; 150 u32 reason_maximum : 1; 151 }; 152 }; 153 154 union { 155 u32 offload_mask; 156 }; 157 } msg_enable_wakeup; 158 159 struct { 160 u32 id; 161 } msg_del_id; 162 }; 163 }; 164 165 struct __packed hw_atl_utils_mbox_header { 166 u32 version; 167 u32 transaction_id; 168 u32 error; 169 }; 170 171 struct __packed hw_aq_info { 172 u8 reserved[6]; 173 u16 phy_fault_code; 174 u16 phy_temperature; 175 u8 cable_len; 176 u8 reserved1; 177 u32 cable_diag_data[4]; 178 u8 reserved2[32]; 179 u32 caps_lo; 180 u32 caps_hi; 181 }; 182 183 struct __packed hw_atl_utils_mbox { 184 struct hw_atl_utils_mbox_header header; 185 struct hw_atl_stats_s stats; 186 struct hw_aq_info info; 187 }; 188 189 /* fw2x */ 190 typedef u32 fw_offset_t; 191 192 struct __packed offload_ip_info { 193 u8 v4_local_addr_count; 194 u8 v4_addr_count; 195 u8 v6_local_addr_count; 196 u8 v6_addr_count; 197 fw_offset_t v4_addr; 198 fw_offset_t v4_prefix; 199 fw_offset_t v6_addr; 200 fw_offset_t v6_prefix; 201 }; 202 203 struct __packed offload_port_info { 204 u16 udp_port_count; 205 u16 tcp_port_count; 206 fw_offset_t udp_port; 207 fw_offset_t tcp_port; 208 }; 209 210 struct __packed offload_ka_info { 211 u16 v4_ka_count; 212 u16 v6_ka_count; 213 u32 retry_count; 214 u32 retry_interval; 215 fw_offset_t v4_ka; 216 fw_offset_t v6_ka; 217 }; 218 219 struct __packed offload_rr_info { 220 u32 rr_count; 221 u32 rr_buf_len; 222 fw_offset_t rr_id_x; 223 fw_offset_t rr_buf; 224 }; 225 226 struct __packed offload_info { 227 u32 version; 228 u32 len; 229 u8 mac_addr[ETH_ALEN]; 230 231 u8 reserved[2]; 232 233 struct offload_ip_info ips; 234 struct offload_port_info ports; 235 struct offload_ka_info kas; 236 struct offload_rr_info rrs; 237 u8 buf[0]; 238 }; 239 240 enum hw_atl_rx_action_with_traffic { 241 HW_ATL_RX_DISCARD, 242 HW_ATL_RX_HOST, 243 }; 244 245 struct aq_rx_filter_vlan { 246 u8 enable; 247 u8 location; 248 u16 vlan_id; 249 u8 queue; 250 }; 251 252 struct aq_rx_filter_l2 { 253 s8 queue; 254 u8 location; 255 u8 user_priority_en; 256 u8 user_priority; 257 u16 ethertype; 258 }; 259 260 struct aq_rx_filter_l3l4 { 261 u32 cmd; 262 u8 location; 263 u32 ip_dst[4]; 264 u32 ip_src[4]; 265 u16 p_dst; 266 u16 p_src; 267 u8 is_ipv6; 268 }; 269 270 enum hw_atl_rx_protocol_value_l3l4 { 271 HW_ATL_RX_TCP, 272 HW_ATL_RX_UDP, 273 HW_ATL_RX_SCTP, 274 HW_ATL_RX_ICMP 275 }; 276 277 enum hw_atl_rx_ctrl_registers_l3l4 { 278 HW_ATL_RX_ENABLE_MNGMNT_QUEUE_L3L4 = BIT(22), 279 HW_ATL_RX_ENABLE_QUEUE_L3L4 = BIT(23), 280 HW_ATL_RX_ENABLE_ARP_FLTR_L3 = BIT(24), 281 HW_ATL_RX_ENABLE_CMP_PROT_L4 = BIT(25), 282 HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 = BIT(26), 283 HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4 = BIT(27), 284 HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3 = BIT(28), 285 HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3 = BIT(29), 286 HW_ATL_RX_ENABLE_L3_IPV6 = BIT(30), 287 HW_ATL_RX_ENABLE_FLTR_L3L4 = BIT(31) 288 }; 289 290 #define HW_ATL_RX_QUEUE_FL3L4_SHIFT 8U 291 #define HW_ATL_RX_ACTION_FL3F4_SHIFT 16U 292 293 #define HW_ATL_RX_CNT_REG_ADDR_IPV6 4U 294 295 #define HW_ATL_GET_REG_LOCATION_FL3L4(location) \ 296 ((location) - AQ_RX_FIRST_LOC_FL3L4) 297 298 #define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U 299 #define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U 300 #define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U 301 #define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U 302 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U 303 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U 304 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 0x04000000U 305 306 #define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \ 307 self->chip_features) 308 309 enum hal_atl_utils_fw_state_e { 310 MPI_DEINIT = 0, 311 MPI_RESET = 1, 312 MPI_INIT = 2, 313 MPI_POWER = 4, 314 }; 315 316 #define HAL_ATLANTIC_RATE_10G BIT(0) 317 #define HAL_ATLANTIC_RATE_5G BIT(1) 318 #define HAL_ATLANTIC_RATE_5GSR BIT(2) 319 #define HAL_ATLANTIC_RATE_2GS BIT(3) 320 #define HAL_ATLANTIC_RATE_1G BIT(4) 321 #define HAL_ATLANTIC_RATE_100M BIT(5) 322 #define HAL_ATLANTIC_RATE_INVALID BIT(6) 323 324 #define HAL_ATLANTIC_UTILS_FW_MSG_PING 0x1U 325 #define HAL_ATLANTIC_UTILS_FW_MSG_ARP 0x2U 326 #define HAL_ATLANTIC_UTILS_FW_MSG_INJECT 0x3U 327 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 0x4U 328 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PRIOR 0x10000000U 329 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PATTERN 0x1U 330 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_MAG_PKT 0x2U 331 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 0x5U 332 #define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 0x6U 333 #define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC 0x7U 334 #define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 0x8U 335 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD 0x9U 336 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL 0xAU 337 #define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG 0xDU 338 339 enum hw_atl_fw2x_rate { 340 FW2X_RATE_100M = 0x20, 341 FW2X_RATE_1G = 0x100, 342 FW2X_RATE_2G5 = 0x200, 343 FW2X_RATE_5G = 0x400, 344 FW2X_RATE_10G = 0x800, 345 }; 346 347 enum hw_atl_fw2x_caps_lo { 348 CAPS_LO_10BASET_HD = 0x00, 349 CAPS_LO_10BASET_FD, 350 CAPS_LO_100BASETX_HD, 351 CAPS_LO_100BASET4_HD, 352 CAPS_LO_100BASET2_HD, 353 CAPS_LO_100BASETX_FD, 354 CAPS_LO_100BASET2_FD, 355 CAPS_LO_1000BASET_HD, 356 CAPS_LO_1000BASET_FD, 357 CAPS_LO_2P5GBASET_FD, 358 CAPS_LO_5GBASET_FD, 359 CAPS_LO_10GBASET_FD, 360 }; 361 362 enum hw_atl_fw2x_caps_hi { 363 CAPS_HI_RESERVED1 = 0x00, 364 CAPS_HI_10BASET_EEE, 365 CAPS_HI_RESERVED2, 366 CAPS_HI_PAUSE, 367 CAPS_HI_ASYMMETRIC_PAUSE, 368 CAPS_HI_100BASETX_EEE, 369 CAPS_HI_RESERVED3, 370 CAPS_HI_RESERVED4, 371 CAPS_HI_1000BASET_FD_EEE, 372 CAPS_HI_2P5GBASET_FD_EEE, 373 CAPS_HI_5GBASET_FD_EEE, 374 CAPS_HI_10GBASET_FD_EEE, 375 CAPS_HI_RESERVED5, 376 CAPS_HI_RESERVED6, 377 CAPS_HI_RESERVED7, 378 CAPS_HI_RESERVED8, 379 CAPS_HI_RESERVED9, 380 CAPS_HI_CABLE_DIAG, 381 CAPS_HI_TEMPERATURE, 382 CAPS_HI_DOWNSHIFT, 383 CAPS_HI_PTP_AVB_EN, 384 CAPS_HI_MEDIA_DETECT, 385 CAPS_HI_LINK_DROP, 386 CAPS_HI_SLEEP_PROXY, 387 CAPS_HI_WOL, 388 CAPS_HI_MAC_STOP, 389 CAPS_HI_EXT_LOOPBACK, 390 CAPS_HI_INT_LOOPBACK, 391 CAPS_HI_EFUSE_AGENT, 392 CAPS_HI_WOL_TIMER, 393 CAPS_HI_STATISTICS, 394 CAPS_HI_TRANSACTION_ID, 395 }; 396 397 enum hw_atl_fw2x_ctrl { 398 CTRL_RESERVED1 = 0x00, 399 CTRL_RESERVED2, 400 CTRL_RESERVED3, 401 CTRL_PAUSE, 402 CTRL_ASYMMETRIC_PAUSE, 403 CTRL_RESERVED4, 404 CTRL_RESERVED5, 405 CTRL_RESERVED6, 406 CTRL_1GBASET_FD_EEE, 407 CTRL_2P5GBASET_FD_EEE, 408 CTRL_5GBASET_FD_EEE, 409 CTRL_10GBASET_FD_EEE, 410 CTRL_THERMAL_SHUTDOWN, 411 CTRL_PHY_LOGS, 412 CTRL_EEE_AUTO_DISABLE, 413 CTRL_PFC, 414 CTRL_WAKE_ON_LINK, 415 CTRL_CABLE_DIAG, 416 CTRL_TEMPERATURE, 417 CTRL_DOWNSHIFT, 418 CTRL_PTP_AVB, 419 CTRL_RESERVED7, 420 CTRL_LINK_DROP, 421 CTRL_SLEEP_PROXY, 422 CTRL_WOL, 423 CTRL_MAC_STOP, 424 CTRL_EXT_LOOPBACK, 425 CTRL_INT_LOOPBACK, 426 CTRL_RESERVED8, 427 CTRL_WOL_TIMER, 428 CTRL_STATISTICS, 429 CTRL_FORCE_RECONNECT, 430 }; 431 432 struct aq_hw_s; 433 struct aq_fw_ops; 434 struct aq_hw_caps_s; 435 struct aq_hw_link_status_s; 436 437 int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops); 438 439 int hw_atl_utils_soft_reset(struct aq_hw_s *self); 440 441 void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p); 442 443 int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self, 444 struct hw_atl_utils_mbox_header *pmbox); 445 446 void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self, 447 struct hw_atl_utils_mbox *pmbox); 448 449 void hw_atl_utils_mpi_set(struct aq_hw_s *self, 450 enum hal_atl_utils_fw_state_e state, 451 u32 speed); 452 453 int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self); 454 455 int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self, 456 u8 *mac); 457 458 unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps); 459 460 int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, 461 const struct aq_hw_caps_s *aq_hw_caps, 462 u32 *regs_buff); 463 464 int hw_atl_utils_hw_set_power(struct aq_hw_s *self, 465 unsigned int power_state); 466 467 int hw_atl_utils_hw_deinit(struct aq_hw_s *self); 468 469 int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version); 470 471 int hw_atl_utils_update_stats(struct aq_hw_s *self); 472 473 struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self); 474 475 int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, 476 u32 *p, u32 cnt); 477 478 int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac); 479 480 int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size); 481 482 int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, 483 struct hw_atl_utils_fw_rpc **rpc); 484 485 extern const struct aq_fw_ops aq_fw_1x_ops; 486 extern const struct aq_fw_ops aq_fw_2x_ops; 487 488 #endif /* HW_ATL_UTILS_H */ 489
