1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/device.h>
3 #include <linux/cpu.h>
4 #include <linux/smp.h>
5 #include <linux/percpu.h>
6 #include <linux/init.h>
7 #include <linux/sched.h>
8 #include <linux/export.h>
9 #include <linux/nodemask.h>
10 #include <linux/cpumask.h>
11 #include <linux/notifier.h>
12
13 #include <asm/current.h>
14 #include <asm/processor.h>
15 #include <asm/cputable.h>
16 #include <asm/hvcall.h>
17 #include <asm/prom.h>
18 #include <asm/machdep.h>
19 #include <asm/smp.h>
20 #include <asm/pmc.h>
21 #include <asm/firmware.h>
22 #include <asm/svm.h>
23
24 #include "cacheinfo.h"
25 #include "setup.h"
26
27 #ifdef CONFIG_PPC64
28 #include <asm/paca.h>
29 #include <asm/lppaca.h>
30 #endif
31
32 static DEFINE_PER_CPU(struct cpu, cpu_devices);
33
34 /*
35 * SMT snooze delay stuff, 64-bit only for now
36 */
37
38 #ifdef CONFIG_PPC64
39
40 /* Time in microseconds we delay before sleeping in the idle loop */
41 static DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
42
store_smt_snooze_delay(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)43 static ssize_t store_smt_snooze_delay(struct device *dev,
44 struct device_attribute *attr,
45 const char *buf,
46 size_t count)
47 {
48 struct cpu *cpu = container_of(dev, struct cpu, dev);
49 ssize_t ret;
50 long snooze;
51
52 ret = sscanf(buf, "%ld", &snooze);
53 if (ret != 1)
54 return -EINVAL;
55
56 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
57 return count;
58 }
59
show_smt_snooze_delay(struct device * dev,struct device_attribute * attr,char * buf)60 static ssize_t show_smt_snooze_delay(struct device *dev,
61 struct device_attribute *attr,
62 char *buf)
63 {
64 struct cpu *cpu = container_of(dev, struct cpu, dev);
65
66 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
67 }
68
69 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
70 store_smt_snooze_delay);
71
setup_smt_snooze_delay(char * str)72 static int __init setup_smt_snooze_delay(char *str)
73 {
74 unsigned int cpu;
75 long snooze;
76
77 if (!cpu_has_feature(CPU_FTR_SMT))
78 return 1;
79
80 snooze = simple_strtol(str, NULL, 10);
81 for_each_possible_cpu(cpu)
82 per_cpu(smt_snooze_delay, cpu) = snooze;
83
84 return 1;
85 }
86 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
87
88 #endif /* CONFIG_PPC64 */
89
90 #ifdef CONFIG_PPC_FSL_BOOK3E
91 #define MAX_BIT 63
92
93 static u64 pw20_wt;
94 static u64 altivec_idle_wt;
95
get_idle_ticks_bit(u64 ns)96 static unsigned int get_idle_ticks_bit(u64 ns)
97 {
98 u64 cycle;
99
100 if (ns >= 10000)
101 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
102 else
103 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
104
105 if (!cycle)
106 return 0;
107
108 return ilog2(cycle);
109 }
110
do_show_pwrmgtcr0(void * val)111 static void do_show_pwrmgtcr0(void *val)
112 {
113 u32 *value = val;
114
115 *value = mfspr(SPRN_PWRMGTCR0);
116 }
117
show_pw20_state(struct device * dev,struct device_attribute * attr,char * buf)118 static ssize_t show_pw20_state(struct device *dev,
119 struct device_attribute *attr, char *buf)
120 {
121 u32 value;
122 unsigned int cpu = dev->id;
123
124 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
125
126 value &= PWRMGTCR0_PW20_WAIT;
127
128 return sprintf(buf, "%u\n", value ? 1 : 0);
129 }
130
do_store_pw20_state(void * val)131 static void do_store_pw20_state(void *val)
132 {
133 u32 *value = val;
134 u32 pw20_state;
135
136 pw20_state = mfspr(SPRN_PWRMGTCR0);
137
138 if (*value)
139 pw20_state |= PWRMGTCR0_PW20_WAIT;
140 else
141 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
142
143 mtspr(SPRN_PWRMGTCR0, pw20_state);
144 }
145
store_pw20_state(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)146 static ssize_t store_pw20_state(struct device *dev,
147 struct device_attribute *attr,
148 const char *buf, size_t count)
149 {
150 u32 value;
151 unsigned int cpu = dev->id;
152
153 if (kstrtou32(buf, 0, &value))
154 return -EINVAL;
155
156 if (value > 1)
157 return -EINVAL;
158
159 smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
160
161 return count;
162 }
163
show_pw20_wait_time(struct device * dev,struct device_attribute * attr,char * buf)164 static ssize_t show_pw20_wait_time(struct device *dev,
165 struct device_attribute *attr, char *buf)
166 {
167 u32 value;
168 u64 tb_cycle = 1;
169 u64 time;
170
171 unsigned int cpu = dev->id;
172
173 if (!pw20_wt) {
174 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
175 value = (value & PWRMGTCR0_PW20_ENT) >>
176 PWRMGTCR0_PW20_ENT_SHIFT;
177
178 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
179 /* convert ms to ns */
180 if (tb_ticks_per_usec > 1000) {
181 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
182 } else {
183 u32 rem_us;
184
185 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
186 &rem_us);
187 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
188 }
189 } else {
190 time = pw20_wt;
191 }
192
193 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
194 }
195
set_pw20_wait_entry_bit(void * val)196 static void set_pw20_wait_entry_bit(void *val)
197 {
198 u32 *value = val;
199 u32 pw20_idle;
200
201 pw20_idle = mfspr(SPRN_PWRMGTCR0);
202
203 /* Set Automatic PW20 Core Idle Count */
204 /* clear count */
205 pw20_idle &= ~PWRMGTCR0_PW20_ENT;
206
207 /* set count */
208 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
209
210 mtspr(SPRN_PWRMGTCR0, pw20_idle);
211 }
212
store_pw20_wait_time(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)213 static ssize_t store_pw20_wait_time(struct device *dev,
214 struct device_attribute *attr,
215 const char *buf, size_t count)
216 {
217 u32 entry_bit;
218 u64 value;
219
220 unsigned int cpu = dev->id;
221
222 if (kstrtou64(buf, 0, &value))
223 return -EINVAL;
224
225 if (!value)
226 return -EINVAL;
227
228 entry_bit = get_idle_ticks_bit(value);
229 if (entry_bit > MAX_BIT)
230 return -EINVAL;
231
232 pw20_wt = value;
233
234 smp_call_function_single(cpu, set_pw20_wait_entry_bit,
235 &entry_bit, 1);
236
237 return count;
238 }
239
show_altivec_idle(struct device * dev,struct device_attribute * attr,char * buf)240 static ssize_t show_altivec_idle(struct device *dev,
241 struct device_attribute *attr, char *buf)
242 {
243 u32 value;
244 unsigned int cpu = dev->id;
245
246 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
247
248 value &= PWRMGTCR0_AV_IDLE_PD_EN;
249
250 return sprintf(buf, "%u\n", value ? 1 : 0);
251 }
252
do_store_altivec_idle(void * val)253 static void do_store_altivec_idle(void *val)
254 {
255 u32 *value = val;
256 u32 altivec_idle;
257
258 altivec_idle = mfspr(SPRN_PWRMGTCR0);
259
260 if (*value)
261 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
262 else
263 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
264
265 mtspr(SPRN_PWRMGTCR0, altivec_idle);
266 }
267
store_altivec_idle(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)268 static ssize_t store_altivec_idle(struct device *dev,
269 struct device_attribute *attr,
270 const char *buf, size_t count)
271 {
272 u32 value;
273 unsigned int cpu = dev->id;
274
275 if (kstrtou32(buf, 0, &value))
276 return -EINVAL;
277
278 if (value > 1)
279 return -EINVAL;
280
281 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
282
283 return count;
284 }
285
show_altivec_idle_wait_time(struct device * dev,struct device_attribute * attr,char * buf)286 static ssize_t show_altivec_idle_wait_time(struct device *dev,
287 struct device_attribute *attr, char *buf)
288 {
289 u32 value;
290 u64 tb_cycle = 1;
291 u64 time;
292
293 unsigned int cpu = dev->id;
294
295 if (!altivec_idle_wt) {
296 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
297 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
298 PWRMGTCR0_AV_IDLE_CNT_SHIFT;
299
300 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
301 /* convert ms to ns */
302 if (tb_ticks_per_usec > 1000) {
303 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
304 } else {
305 u32 rem_us;
306
307 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
308 &rem_us);
309 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
310 }
311 } else {
312 time = altivec_idle_wt;
313 }
314
315 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
316 }
317
set_altivec_idle_wait_entry_bit(void * val)318 static void set_altivec_idle_wait_entry_bit(void *val)
319 {
320 u32 *value = val;
321 u32 altivec_idle;
322
323 altivec_idle = mfspr(SPRN_PWRMGTCR0);
324
325 /* Set Automatic AltiVec Idle Count */
326 /* clear count */
327 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
328
329 /* set count */
330 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
331
332 mtspr(SPRN_PWRMGTCR0, altivec_idle);
333 }
334
store_altivec_idle_wait_time(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)335 static ssize_t store_altivec_idle_wait_time(struct device *dev,
336 struct device_attribute *attr,
337 const char *buf, size_t count)
338 {
339 u32 entry_bit;
340 u64 value;
341
342 unsigned int cpu = dev->id;
343
344 if (kstrtou64(buf, 0, &value))
345 return -EINVAL;
346
347 if (!value)
348 return -EINVAL;
349
350 entry_bit = get_idle_ticks_bit(value);
351 if (entry_bit > MAX_BIT)
352 return -EINVAL;
353
354 altivec_idle_wt = value;
355
356 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
357 &entry_bit, 1);
358
359 return count;
360 }
361
362 /*
363 * Enable/Disable interface:
364 * 0, disable. 1, enable.
365 */
366 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
367 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
368
369 /*
370 * Set wait time interface:(Nanosecond)
371 * Example: Base on TBfreq is 41MHZ.
372 * 1~48(ns): TB[63]
373 * 49~97(ns): TB[62]
374 * 98~195(ns): TB[61]
375 * 196~390(ns): TB[60]
376 * 391~780(ns): TB[59]
377 * 781~1560(ns): TB[58]
378 * ...
379 */
380 static DEVICE_ATTR(pw20_wait_time, 0600,
381 show_pw20_wait_time,
382 store_pw20_wait_time);
383 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
384 show_altivec_idle_wait_time,
385 store_altivec_idle_wait_time);
386 #endif
387
388 /*
389 * Enabling PMCs will slow partition context switch times so we only do
390 * it the first time we write to the PMCs.
391 */
392
393 static DEFINE_PER_CPU(char, pmcs_enabled);
394
ppc_enable_pmcs(void)395 void ppc_enable_pmcs(void)
396 {
397 ppc_set_pmu_inuse(1);
398
399 /* Only need to enable them once */
400 if (__this_cpu_read(pmcs_enabled))
401 return;
402
403 __this_cpu_write(pmcs_enabled, 1);
404
405 if (ppc_md.enable_pmcs)
406 ppc_md.enable_pmcs();
407 }
408 EXPORT_SYMBOL(ppc_enable_pmcs);
409
410 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
411 static void read_##NAME(void *val) \
412 { \
413 *(unsigned long *)val = mfspr(ADDRESS); \
414 } \
415 static void write_##NAME(void *val) \
416 { \
417 EXTRA; \
418 mtspr(ADDRESS, *(unsigned long *)val); \
419 }
420
421 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
422 static ssize_t show_##NAME(struct device *dev, \
423 struct device_attribute *attr, \
424 char *buf) \
425 { \
426 struct cpu *cpu = container_of(dev, struct cpu, dev); \
427 unsigned long val; \
428 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
429 return sprintf(buf, "%lx\n", val); \
430 } \
431 static ssize_t __used \
432 store_##NAME(struct device *dev, struct device_attribute *attr, \
433 const char *buf, size_t count) \
434 { \
435 struct cpu *cpu = container_of(dev, struct cpu, dev); \
436 unsigned long val; \
437 int ret = sscanf(buf, "%lx", &val); \
438 if (ret != 1) \
439 return -EINVAL; \
440 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
441 return count; \
442 }
443
444 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
445 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
446 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
447 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
448 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
449 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
450
451 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
452 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
453
454 /* Let's define all possible registers, we'll only hook up the ones
455 * that are implemented on the current processor
456 */
457
458 #if defined(CONFIG_PPC64)
459 #define HAS_PPC_PMC_CLASSIC 1
460 #define HAS_PPC_PMC_IBM 1
461 #define HAS_PPC_PMC_PA6T 1
462 #elif defined(CONFIG_PPC_BOOK3S_32)
463 #define HAS_PPC_PMC_CLASSIC 1
464 #define HAS_PPC_PMC_IBM 1
465 #define HAS_PPC_PMC_G4 1
466 #endif
467
468
469 #ifdef HAS_PPC_PMC_CLASSIC
470 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
471 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
472 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
473 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
474 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
475 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
476 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
477 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
478
479 #ifdef HAS_PPC_PMC_G4
480 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
481 #endif
482
483 #ifdef CONFIG_PPC64
484 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
485 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
486
487 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
488 SYSFS_SPRSETUP(purr, SPRN_PURR);
489 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
490 SYSFS_SPRSETUP(pir, SPRN_PIR);
491 SYSFS_SPRSETUP(tscr, SPRN_TSCR);
492
493 /*
494 Lets only enable read for phyp resources and
495 enable write when needed with a separate function.
496 Lets be conservative and default to pseries.
497 */
498 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
499 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
500 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
501 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
502 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
503
504 /*
505 * This is the system wide DSCR register default value. Any
506 * change to this default value through the sysfs interface
507 * will update all per cpu DSCR default values across the
508 * system stored in their respective PACA structures.
509 */
510 static unsigned long dscr_default;
511
512 /**
513 * read_dscr() - Fetch the cpu specific DSCR default
514 * @val: Returned cpu specific DSCR default value
515 *
516 * This function returns the per cpu DSCR default value
517 * for any cpu which is contained in it's PACA structure.
518 */
read_dscr(void * val)519 static void read_dscr(void *val)
520 {
521 *(unsigned long *)val = get_paca()->dscr_default;
522 }
523
524
525 /**
526 * write_dscr() - Update the cpu specific DSCR default
527 * @val: New cpu specific DSCR default value to update
528 *
529 * This function updates the per cpu DSCR default value
530 * for any cpu which is contained in it's PACA structure.
531 */
write_dscr(void * val)532 static void write_dscr(void *val)
533 {
534 get_paca()->dscr_default = *(unsigned long *)val;
535 if (!current->thread.dscr_inherit) {
536 current->thread.dscr = *(unsigned long *)val;
537 mtspr(SPRN_DSCR, *(unsigned long *)val);
538 }
539 }
540
541 SYSFS_SPRSETUP_SHOW_STORE(dscr);
542 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
543
add_write_permission_dev_attr(struct device_attribute * attr)544 static void add_write_permission_dev_attr(struct device_attribute *attr)
545 {
546 attr->attr.mode |= 0200;
547 }
548
549 /**
550 * show_dscr_default() - Fetch the system wide DSCR default
551 * @dev: Device structure
552 * @attr: Device attribute structure
553 * @buf: Interface buffer
554 *
555 * This function returns the system wide DSCR default value.
556 */
show_dscr_default(struct device * dev,struct device_attribute * attr,char * buf)557 static ssize_t show_dscr_default(struct device *dev,
558 struct device_attribute *attr, char *buf)
559 {
560 return sprintf(buf, "%lx\n", dscr_default);
561 }
562
563 /**
564 * store_dscr_default() - Update the system wide DSCR default
565 * @dev: Device structure
566 * @attr: Device attribute structure
567 * @buf: Interface buffer
568 * @count: Size of the update
569 *
570 * This function updates the system wide DSCR default value.
571 */
store_dscr_default(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)572 static ssize_t __used store_dscr_default(struct device *dev,
573 struct device_attribute *attr, const char *buf,
574 size_t count)
575 {
576 unsigned long val;
577 int ret = 0;
578
579 ret = sscanf(buf, "%lx", &val);
580 if (ret != 1)
581 return -EINVAL;
582 dscr_default = val;
583
584 on_each_cpu(write_dscr, &val, 1);
585
586 return count;
587 }
588
589 static DEVICE_ATTR(dscr_default, 0600,
590 show_dscr_default, store_dscr_default);
591
sysfs_create_dscr_default(void)592 static void sysfs_create_dscr_default(void)
593 {
594 if (cpu_has_feature(CPU_FTR_DSCR)) {
595 int err = 0;
596 int cpu;
597
598 dscr_default = spr_default_dscr;
599 for_each_possible_cpu(cpu)
600 paca_ptrs[cpu]->dscr_default = dscr_default;
601
602 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
603 }
604 }
605
606 #endif /* CONFIG_PPC64 */
607
608 #ifdef HAS_PPC_PMC_PA6T
609 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
610 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
611 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
612 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
613 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
614 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
615 #ifdef CONFIG_DEBUG_MISC
616 SYSFS_SPRSETUP(hid0, SPRN_HID0);
617 SYSFS_SPRSETUP(hid1, SPRN_HID1);
618 SYSFS_SPRSETUP(hid4, SPRN_HID4);
619 SYSFS_SPRSETUP(hid5, SPRN_HID5);
620 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
621 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
622 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
623 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
624 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
625 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
626 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
627 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
628 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
629 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
630 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
631 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
632 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
633 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
634 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
635 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
636 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
637 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
638 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
639 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
640 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
641 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
642 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
643 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
644 #endif /* CONFIG_DEBUG_MISC */
645 #endif /* HAS_PPC_PMC_PA6T */
646
647 #ifdef HAS_PPC_PMC_IBM
648 static struct device_attribute ibm_common_attrs[] = {
649 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
650 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
651 };
652 #endif /* HAS_PPC_PMC_G4 */
653
654 #ifdef HAS_PPC_PMC_G4
655 static struct device_attribute g4_common_attrs[] = {
656 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
657 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
658 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
659 };
660 #endif /* HAS_PPC_PMC_G4 */
661
662 static struct device_attribute classic_pmc_attrs[] = {
663 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
664 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
665 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
666 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
667 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
668 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
669 #ifdef CONFIG_PPC64
670 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
671 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
672 #endif
673 };
674
675 #ifdef HAS_PPC_PMC_PA6T
676 static struct device_attribute pa6t_attrs[] = {
677 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
678 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
679 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
680 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
681 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
682 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
683 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
684 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
685 #ifdef CONFIG_DEBUG_MISC
686 __ATTR(hid0, 0600, show_hid0, store_hid0),
687 __ATTR(hid1, 0600, show_hid1, store_hid1),
688 __ATTR(hid4, 0600, show_hid4, store_hid4),
689 __ATTR(hid5, 0600, show_hid5, store_hid5),
690 __ATTR(ima0, 0600, show_ima0, store_ima0),
691 __ATTR(ima1, 0600, show_ima1, store_ima1),
692 __ATTR(ima2, 0600, show_ima2, store_ima2),
693 __ATTR(ima3, 0600, show_ima3, store_ima3),
694 __ATTR(ima4, 0600, show_ima4, store_ima4),
695 __ATTR(ima5, 0600, show_ima5, store_ima5),
696 __ATTR(ima6, 0600, show_ima6, store_ima6),
697 __ATTR(ima7, 0600, show_ima7, store_ima7),
698 __ATTR(ima8, 0600, show_ima8, store_ima8),
699 __ATTR(ima9, 0600, show_ima9, store_ima9),
700 __ATTR(imaat, 0600, show_imaat, store_imaat),
701 __ATTR(btcr, 0600, show_btcr, store_btcr),
702 __ATTR(pccr, 0600, show_pccr, store_pccr),
703 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
704 __ATTR(der, 0600, show_der, store_der),
705 __ATTR(mer, 0600, show_mer, store_mer),
706 __ATTR(ber, 0600, show_ber, store_ber),
707 __ATTR(ier, 0600, show_ier, store_ier),
708 __ATTR(sier, 0600, show_sier, store_sier),
709 __ATTR(siar, 0600, show_siar, store_siar),
710 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
711 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
712 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
713 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
714 #endif /* CONFIG_DEBUG_MISC */
715 };
716 #endif /* HAS_PPC_PMC_PA6T */
717 #endif /* HAS_PPC_PMC_CLASSIC */
718
719 #ifdef CONFIG_PPC_SVM
show_svm(struct device * dev,struct device_attribute * attr,char * buf)720 static ssize_t show_svm(struct device *dev, struct device_attribute *attr, char *buf)
721 {
722 return sprintf(buf, "%u\n", is_secure_guest());
723 }
724 static DEVICE_ATTR(svm, 0444, show_svm, NULL);
725
create_svm_file(void)726 static void create_svm_file(void)
727 {
728 device_create_file(cpu_subsys.dev_root, &dev_attr_svm);
729 }
730 #else
create_svm_file(void)731 static void create_svm_file(void)
732 {
733 }
734 #endif /* CONFIG_PPC_SVM */
735
register_cpu_online(unsigned int cpu)736 static int register_cpu_online(unsigned int cpu)
737 {
738 struct cpu *c = &per_cpu(cpu_devices, cpu);
739 struct device *s = &c->dev;
740 struct device_attribute *attrs, *pmc_attrs;
741 int i, nattrs;
742
743 /* For cpus present at boot a reference was already grabbed in register_cpu() */
744 if (!s->of_node)
745 s->of_node = of_get_cpu_node(cpu, NULL);
746
747 #ifdef CONFIG_PPC64
748 if (cpu_has_feature(CPU_FTR_SMT))
749 device_create_file(s, &dev_attr_smt_snooze_delay);
750 #endif
751
752 /* PMC stuff */
753 switch (cur_cpu_spec->pmc_type) {
754 #ifdef HAS_PPC_PMC_IBM
755 case PPC_PMC_IBM:
756 attrs = ibm_common_attrs;
757 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
758 pmc_attrs = classic_pmc_attrs;
759 break;
760 #endif /* HAS_PPC_PMC_IBM */
761 #ifdef HAS_PPC_PMC_G4
762 case PPC_PMC_G4:
763 attrs = g4_common_attrs;
764 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
765 pmc_attrs = classic_pmc_attrs;
766 break;
767 #endif /* HAS_PPC_PMC_G4 */
768 #ifdef HAS_PPC_PMC_PA6T
769 case PPC_PMC_PA6T:
770 /* PA Semi starts counting at PMC0 */
771 attrs = pa6t_attrs;
772 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
773 pmc_attrs = NULL;
774 break;
775 #endif /* HAS_PPC_PMC_PA6T */
776 default:
777 attrs = NULL;
778 nattrs = 0;
779 pmc_attrs = NULL;
780 }
781
782 for (i = 0; i < nattrs; i++)
783 device_create_file(s, &attrs[i]);
784
785 if (pmc_attrs)
786 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
787 device_create_file(s, &pmc_attrs[i]);
788
789 #ifdef CONFIG_PPC64
790 if (cpu_has_feature(CPU_FTR_MMCRA))
791 device_create_file(s, &dev_attr_mmcra);
792
793 if (cpu_has_feature(CPU_FTR_PURR)) {
794 if (!firmware_has_feature(FW_FEATURE_LPAR))
795 add_write_permission_dev_attr(&dev_attr_purr);
796 device_create_file(s, &dev_attr_purr);
797 }
798
799 if (cpu_has_feature(CPU_FTR_SPURR))
800 device_create_file(s, &dev_attr_spurr);
801
802 if (cpu_has_feature(CPU_FTR_DSCR))
803 device_create_file(s, &dev_attr_dscr);
804
805 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
806 device_create_file(s, &dev_attr_pir);
807
808 if (cpu_has_feature(CPU_FTR_ARCH_206) &&
809 !firmware_has_feature(FW_FEATURE_LPAR))
810 device_create_file(s, &dev_attr_tscr);
811 #endif /* CONFIG_PPC64 */
812
813 #ifdef CONFIG_PPC_FSL_BOOK3E
814 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
815 device_create_file(s, &dev_attr_pw20_state);
816 device_create_file(s, &dev_attr_pw20_wait_time);
817
818 device_create_file(s, &dev_attr_altivec_idle);
819 device_create_file(s, &dev_attr_altivec_idle_wait_time);
820 }
821 #endif
822 cacheinfo_cpu_online(cpu);
823 return 0;
824 }
825
826 #ifdef CONFIG_HOTPLUG_CPU
unregister_cpu_online(unsigned int cpu)827 static int unregister_cpu_online(unsigned int cpu)
828 {
829 struct cpu *c = &per_cpu(cpu_devices, cpu);
830 struct device *s = &c->dev;
831 struct device_attribute *attrs, *pmc_attrs;
832 int i, nattrs;
833
834 BUG_ON(!c->hotpluggable);
835
836 #ifdef CONFIG_PPC64
837 if (cpu_has_feature(CPU_FTR_SMT))
838 device_remove_file(s, &dev_attr_smt_snooze_delay);
839 #endif
840
841 /* PMC stuff */
842 switch (cur_cpu_spec->pmc_type) {
843 #ifdef HAS_PPC_PMC_IBM
844 case PPC_PMC_IBM:
845 attrs = ibm_common_attrs;
846 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
847 pmc_attrs = classic_pmc_attrs;
848 break;
849 #endif /* HAS_PPC_PMC_IBM */
850 #ifdef HAS_PPC_PMC_G4
851 case PPC_PMC_G4:
852 attrs = g4_common_attrs;
853 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
854 pmc_attrs = classic_pmc_attrs;
855 break;
856 #endif /* HAS_PPC_PMC_G4 */
857 #ifdef HAS_PPC_PMC_PA6T
858 case PPC_PMC_PA6T:
859 /* PA Semi starts counting at PMC0 */
860 attrs = pa6t_attrs;
861 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
862 pmc_attrs = NULL;
863 break;
864 #endif /* HAS_PPC_PMC_PA6T */
865 default:
866 attrs = NULL;
867 nattrs = 0;
868 pmc_attrs = NULL;
869 }
870
871 for (i = 0; i < nattrs; i++)
872 device_remove_file(s, &attrs[i]);
873
874 if (pmc_attrs)
875 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
876 device_remove_file(s, &pmc_attrs[i]);
877
878 #ifdef CONFIG_PPC64
879 if (cpu_has_feature(CPU_FTR_MMCRA))
880 device_remove_file(s, &dev_attr_mmcra);
881
882 if (cpu_has_feature(CPU_FTR_PURR))
883 device_remove_file(s, &dev_attr_purr);
884
885 if (cpu_has_feature(CPU_FTR_SPURR))
886 device_remove_file(s, &dev_attr_spurr);
887
888 if (cpu_has_feature(CPU_FTR_DSCR))
889 device_remove_file(s, &dev_attr_dscr);
890
891 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
892 device_remove_file(s, &dev_attr_pir);
893
894 if (cpu_has_feature(CPU_FTR_ARCH_206) &&
895 !firmware_has_feature(FW_FEATURE_LPAR))
896 device_remove_file(s, &dev_attr_tscr);
897 #endif /* CONFIG_PPC64 */
898
899 #ifdef CONFIG_PPC_FSL_BOOK3E
900 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
901 device_remove_file(s, &dev_attr_pw20_state);
902 device_remove_file(s, &dev_attr_pw20_wait_time);
903
904 device_remove_file(s, &dev_attr_altivec_idle);
905 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
906 }
907 #endif
908 cacheinfo_cpu_offline(cpu);
909 of_node_put(s->of_node);
910 s->of_node = NULL;
911 return 0;
912 }
913 #else /* !CONFIG_HOTPLUG_CPU */
914 #define unregister_cpu_online NULL
915 #endif
916
917 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
arch_cpu_probe(const char * buf,size_t count)918 ssize_t arch_cpu_probe(const char *buf, size_t count)
919 {
920 if (ppc_md.cpu_probe)
921 return ppc_md.cpu_probe(buf, count);
922
923 return -EINVAL;
924 }
925
arch_cpu_release(const char * buf,size_t count)926 ssize_t arch_cpu_release(const char *buf, size_t count)
927 {
928 if (ppc_md.cpu_release)
929 return ppc_md.cpu_release(buf, count);
930
931 return -EINVAL;
932 }
933 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
934
935 static DEFINE_MUTEX(cpu_mutex);
936
cpu_add_dev_attr(struct device_attribute * attr)937 int cpu_add_dev_attr(struct device_attribute *attr)
938 {
939 int cpu;
940
941 mutex_lock(&cpu_mutex);
942
943 for_each_possible_cpu(cpu) {
944 device_create_file(get_cpu_device(cpu), attr);
945 }
946
947 mutex_unlock(&cpu_mutex);
948 return 0;
949 }
950 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
951
cpu_add_dev_attr_group(struct attribute_group * attrs)952 int cpu_add_dev_attr_group(struct attribute_group *attrs)
953 {
954 int cpu;
955 struct device *dev;
956 int ret;
957
958 mutex_lock(&cpu_mutex);
959
960 for_each_possible_cpu(cpu) {
961 dev = get_cpu_device(cpu);
962 ret = sysfs_create_group(&dev->kobj, attrs);
963 WARN_ON(ret != 0);
964 }
965
966 mutex_unlock(&cpu_mutex);
967 return 0;
968 }
969 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
970
971
cpu_remove_dev_attr(struct device_attribute * attr)972 void cpu_remove_dev_attr(struct device_attribute *attr)
973 {
974 int cpu;
975
976 mutex_lock(&cpu_mutex);
977
978 for_each_possible_cpu(cpu) {
979 device_remove_file(get_cpu_device(cpu), attr);
980 }
981
982 mutex_unlock(&cpu_mutex);
983 }
984 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
985
cpu_remove_dev_attr_group(struct attribute_group * attrs)986 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
987 {
988 int cpu;
989 struct device *dev;
990
991 mutex_lock(&cpu_mutex);
992
993 for_each_possible_cpu(cpu) {
994 dev = get_cpu_device(cpu);
995 sysfs_remove_group(&dev->kobj, attrs);
996 }
997
998 mutex_unlock(&cpu_mutex);
999 }
1000 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
1001
1002
1003 /* NUMA stuff */
1004
1005 #ifdef CONFIG_NUMA
register_nodes(void)1006 static void register_nodes(void)
1007 {
1008 int i;
1009
1010 for (i = 0; i < MAX_NUMNODES; i++)
1011 register_one_node(i);
1012 }
1013
sysfs_add_device_to_node(struct device * dev,int nid)1014 int sysfs_add_device_to_node(struct device *dev, int nid)
1015 {
1016 struct node *node = node_devices[nid];
1017 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
1018 kobject_name(&dev->kobj));
1019 }
1020 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
1021
sysfs_remove_device_from_node(struct device * dev,int nid)1022 void sysfs_remove_device_from_node(struct device *dev, int nid)
1023 {
1024 struct node *node = node_devices[nid];
1025 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1026 }
1027 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1028
1029 #else
register_nodes(void)1030 static void register_nodes(void)
1031 {
1032 return;
1033 }
1034
1035 #endif
1036
1037 /* Only valid if CPU is present. */
show_physical_id(struct device * dev,struct device_attribute * attr,char * buf)1038 static ssize_t show_physical_id(struct device *dev,
1039 struct device_attribute *attr, char *buf)
1040 {
1041 struct cpu *cpu = container_of(dev, struct cpu, dev);
1042
1043 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1044 }
1045 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1046
topology_init(void)1047 static int __init topology_init(void)
1048 {
1049 int cpu, r;
1050
1051 register_nodes();
1052
1053 for_each_possible_cpu(cpu) {
1054 struct cpu *c = &per_cpu(cpu_devices, cpu);
1055
1056 /*
1057 * For now, we just see if the system supports making
1058 * the RTAS calls for CPU hotplug. But, there may be a
1059 * more comprehensive way to do this for an individual
1060 * CPU. For instance, the boot cpu might never be valid
1061 * for hotplugging.
1062 */
1063 if (ppc_md.cpu_die)
1064 c->hotpluggable = 1;
1065
1066 if (cpu_online(cpu) || c->hotpluggable) {
1067 register_cpu(c, cpu);
1068
1069 device_create_file(&c->dev, &dev_attr_physical_id);
1070 }
1071 }
1072 r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1073 register_cpu_online, unregister_cpu_online);
1074 WARN_ON(r < 0);
1075 #ifdef CONFIG_PPC64
1076 sysfs_create_dscr_default();
1077 #endif /* CONFIG_PPC64 */
1078
1079 create_svm_file();
1080
1081 return 0;
1082 }
1083 subsys_initcall(topology_init);
1084
