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/Linux-v5.4/arch/arm/net/
Dbpf_jit_32.h159 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) argument
161 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument
165 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
166 #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) argument
167 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
168 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument
169 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
170 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument
172 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
173 #define ARM_ANDS_R(rd, rn, rm) _AL3_R(ARM_INST_ANDS, rd, rn, rm) argument
[all …]
Dbpf_jit_32.c414 static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx) in emit_mov_i_no8m() argument
417 emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx); in emit_mov_i_no8m()
419 emit(ARM_MOVW(rd, val & 0xffff), ctx); in emit_mov_i_no8m()
421 emit(ARM_MOVT(rd, val >> 16), ctx); in emit_mov_i_no8m()
425 static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx) in emit_mov_i() argument
430 emit(ARM_MOV_I(rd, imm12), ctx); in emit_mov_i()
432 emit_mov_i_no8m(rd, val, ctx); in emit_mov_i()
465 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op) in emit_udivmod() argument
472 emit(ARM_UDIV(rd, rm, rn), ctx); in emit_udivmod()
475 emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx); in emit_udivmod()
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/Linux-v5.4/arch/arm/include/debug/
Dsamsung.S12 .macro fifo_level_s5pv210 rd, rx
13 ldr \rd, [\rx, # S3C2410_UFSTAT]
14 ARM_BE8(rev \rd, \rd)
15 and \rd, \rd, #S5PV210_UFSTAT_TXMASK
18 .macro fifo_full_s5pv210 rd, rx
19 ldr \rd, [\rx, # S3C2410_UFSTAT]
20 ARM_BE8(rev \rd, \rd)
21 tst \rd, #S5PV210_UFSTAT_TXFULL
27 .macro fifo_level_s3c2440 rd, rx
28 ldr \rd, [\rx, # S3C2410_UFSTAT]
[all …]
D8250.S15 .macro store, rd, rx:vararg
16 ARM_BE8(rev \rd, \rd)
17 str \rd, \rx
18 ARM_BE8(rev \rd, \rd)
21 .macro load, rd, rx:vararg
22 ldr \rd, \rx
23 ARM_BE8(rev \rd, \rd)
26 .macro store, rd, rx:vararg
27 strb \rd, \rx
30 .macro load, rd, rx:vararg
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Dmsm.S14 .macro senduart, rd, rx
15 ARM_BE8(rev \rd, \rd )
17 str \rd, [\rx, #0x70]
20 .macro waituart, rd, rx
22 ldr \rd, [\rx, #0x08]
23 ARM_BE8(rev \rd, \rd )
24 tst \rd, #0x08
27 1001: ldr \rd, [\rx, #0x14]
28 ARM_BE8(rev \rd, \rd )
29 tst \rd, #0x80
[all …]
Dicedcc.S15 .macro senduart, rd, rx
16 mcr p14, 0, \rd, c0, c5, 0
19 .macro busyuart, rd, rx
26 .macro waituart, rd, rx
27 mov \rd, #0x2000000
29 subs \rd, \rd, #1
39 .macro senduart, rd, rx
40 mcr p14, 0, \rd, c8, c0, 0
43 .macro busyuart, rd, rx
50 .macro waituart, rd, rx
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Dpl01x.S25 .macro senduart,rd,rx
26 strb \rd, [\rx, #UART01x_DR]
29 .macro waituart,rd,rx
30 1001: ldr \rd, [\rx, #UART01x_FR]
31 ARM_BE8( rev \rd, \rd )
32 tst \rd, #UART01x_FR_TXFF
36 .macro busyuart,rd,rx
37 1001: ldr \rd, [\rx, #UART01x_FR]
38 ARM_BE8( rev \rd, \rd )
39 tst \rd, #UART01x_FR_BUSY
Drenesas-scif.S36 .macro waituart, rd, rx
37 1001: ldrh \rd, [\rx, #FSR]
38 tst \rd, #TDFE
42 .macro senduart, rd, rx
43 strb \rd, [\rx, #FTDR]
44 ldrh \rd, [\rx, #FSR]
45 bic \rd, \rd, #TEND
46 strh \rd, [\rx, #FSR]
49 .macro busyuart, rd, rx
50 1001: ldrh \rd, [\rx, #FSR]
[all …]
Dzynq.S32 .macro senduart,rd,rx
33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
36 .macro waituart,rd,rx
37 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
38 ARM_BE8( rev \rd, \rd )
39 tst \rd, #UART_SR_TXEMPTY
43 .macro busyuart,rd,rx
44 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
45 ARM_BE8( rev \rd, \rd )
46 tst \rd, #UART_SR_TXFULL @
Domap2plus.S63 .macro senduart,rd,rx
64 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
66 strb \rd, [\rx] @ send lower byte of rd
67 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
68 bic \rd, \rd, #(0xff << 24) @ restore original rd
71 .macro busyuart,rd,rx
72 1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
73 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
74 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
78 .macro waituart,rd,rx
Dimx.S33 .macro senduart,rd,rx
34 ARM_BE8(rev \rd, \rd)
35 str \rd, [\rx, #0x40] @ TXDATA
38 .macro waituart,rd,rx
41 .macro busyuart,rd,rx
42 1002: ldr \rd, [\rx, #0x98] @ SR2
43 ARM_BE8(rev \rd, \rd)
44 tst \rd, #1 << 3 @ TXDC
/Linux-v5.4/arch/riscv/net/
Dbpf_jit_comp.c162 static u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_r_insn() argument
165 (rd << 7) | opcode; in rv_r_insn()
168 static u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument
170 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn()
191 static u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode) in rv_u_insn() argument
193 return (imm31_12 << 12) | (rd << 7) | opcode; in rv_u_insn()
196 static u32 rv_uj_insn(u32 imm20_1, u8 rd, u8 opcode) in rv_uj_insn() argument
203 return (imm << 12) | (rd << 7) | opcode; in rv_uj_insn()
207 u8 funct3, u8 rd, u8 opcode) in rv_amo_insn() argument
211 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); in rv_amo_insn()
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/Linux-v5.4/drivers/gpu/drm/msm/
Dmsm_rd.c101 static void rd_write(struct msm_rd_state *rd, const void *buf, int sz) in rd_write() argument
103 struct circ_buf *fifo = &rd->fifo; in rd_write()
110 wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0 || !rd->open); in rd_write()
111 if (!rd->open) in rd_write()
118 n = min(sz, circ_space_to_end(&rd->fifo)); in rd_write()
125 wake_up_all(&rd->fifo_event); in rd_write()
129 static void rd_write_section(struct msm_rd_state *rd, in rd_write_section() argument
132 rd_write(rd, &type, 4); in rd_write_section()
133 rd_write(rd, &sz, 4); in rd_write_section()
134 rd_write(rd, buf, sz); in rd_write_section()
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/Linux-v5.4/drivers/powercap/
Dintel_rapl_common.c95 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
131 static int rapl_read_data_raw(struct rapl_domain *rd,
134 static int rapl_write_data_raw(struct rapl_domain *rd,
137 static u64 rapl_unit_xlate(struct rapl_domain *rd,
154 struct rapl_domain *rd; in get_energy_counter() local
161 rd = power_zone_to_rapl_domain(power_zone); in get_energy_counter()
163 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) { in get_energy_counter()
176 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev); in get_max_energy_counter() local
178 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); in get_max_energy_counter()
184 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); in release_zone() local
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/Linux-v5.4/kernel/time/
Dsched_clock.c100 struct clock_read_data *rd; in sched_clock() local
104 rd = cd.read_data + (seq & 1); in sched_clock()
106 cyc = (rd->read_sched_clock() - rd->epoch_cyc) & in sched_clock()
107 rd->sched_clock_mask; in sched_clock()
108 res = rd->epoch_ns + cyc_to_ns(cyc, rd->mult, rd->shift); in sched_clock()
124 static void update_clock_read_data(struct clock_read_data *rd) in update_clock_read_data() argument
127 cd.read_data[1] = *rd; in update_clock_read_data()
133 cd.read_data[0] = *rd; in update_clock_read_data()
146 struct clock_read_data rd; in update_sched_clock() local
148 rd = cd.read_data[0]; in update_sched_clock()
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/Linux-v5.4/fs/jffs2/
Dwrite.c206 struct jffs2_raw_dirent *rd, const unsigned char *name, in jffs2_write_dirent() argument
218 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent()
219 je32_to_cpu(rd->name_crc)); in jffs2_write_dirent()
221 D1(if(je32_to_cpu(rd->hdr_crc) != crc32(0, rd, sizeof(struct jffs2_unknown_node)-4)) { in jffs2_write_dirent()
231 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent()
232 je32_to_cpu(rd->name_crc)); in jffs2_write_dirent()
237 vecs[0].iov_base = rd; in jffs2_write_dirent()
238 vecs[0].iov_len = sizeof(*rd); in jffs2_write_dirent()
246 fd->version = je32_to_cpu(rd->version); in jffs2_write_dirent()
247 fd->ino = je32_to_cpu(rd->ino); in jffs2_write_dirent()
[all …]
Ddir.c285 struct jffs2_raw_dirent *rd; in jffs2_symlink() local
379 ret = jffs2_reserve_space(c, sizeof(*rd)+namelen, &alloclen, in jffs2_symlink()
384 rd = jffs2_alloc_raw_dirent(); in jffs2_symlink()
385 if (!rd) { in jffs2_symlink()
395 rd->magic = cpu_to_je16(JFFS2_MAGIC_BITMASK); in jffs2_symlink()
396 rd->nodetype = cpu_to_je16(JFFS2_NODETYPE_DIRENT); in jffs2_symlink()
397 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_symlink()
398 rd->hdr_crc = cpu_to_je32(crc32(0, rd, sizeof(struct jffs2_unknown_node)-4)); in jffs2_symlink()
400 rd->pino = cpu_to_je32(dir_i->i_ino); in jffs2_symlink()
401 rd->version = cpu_to_je32(++dir_f->highest_version); in jffs2_symlink()
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/Linux-v5.4/arch/sparc/include/asm/
Dhead_32.h13 rd %psr, %l0; b label; rd %wim, %l3; nop;
16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
38 rd %psr, %l0;
42 rd %psr,%l0; \
50 rd %psr,%l0; \
59 b getcc_trap_handler; rd %psr, %l0; nop; nop;
63 b setcc_trap_handler; rd %psr, %l0; nop; nop;
67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
[all …]
/Linux-v5.4/drivers/media/tuners/
Dqt1010.c51 qt1010_i2c_oper_t rd[48] = { in qt1010_set_params() local
123 rd[2].val = reg05; in qt1010_set_params()
126 rd[4].val = (freq + QT1010_OFFSET) / FREQ1; in qt1010_set_params()
129 if (mod1 < 8000000) rd[6].val = 0x1d; in qt1010_set_params()
130 else rd[6].val = 0x1c; in qt1010_set_params()
133 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ in qt1010_set_params()
134 else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */ in qt1010_set_params()
135 else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /* +8 MHz */ in qt1010_set_params()
136 else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */ in qt1010_set_params()
137 else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */ in qt1010_set_params()
[all …]
/Linux-v5.4/drivers/reset/
Dreset-pistachio.c66 struct pistachio_reset_data *rd; in pistachio_reset_assert() local
70 rd = container_of(rcdev, struct pistachio_reset_data, rcdev); in pistachio_reset_assert()
76 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_assert()
83 struct pistachio_reset_data *rd; in pistachio_reset_deassert() local
87 rd = container_of(rcdev, struct pistachio_reset_data, rcdev); in pistachio_reset_deassert()
93 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_deassert()
104 struct pistachio_reset_data *rd; in pistachio_reset_probe() local
108 rd = devm_kzalloc(dev, sizeof(*rd), GFP_KERNEL); in pistachio_reset_probe()
109 if (!rd) in pistachio_reset_probe()
112 rd->periph_regs = syscon_node_to_regmap(np->parent); in pistachio_reset_probe()
[all …]
/Linux-v5.4/arch/unicore32/mm/
Dproc-macros.S38 .macro vma_vm_mm, rd, rn
39 ldw \rd, [\rn+], #VMA_VM_MM
45 .macro vma_vm_flags, rd, rn
46 ldw \rd, [\rn+], #VMA_VM_FLAGS
49 .macro tsk_mm, rd, rn
50 ldw \rd, [\rn+], #TI_TASK
51 ldw \rd, [\rd+], #TSK_ACTIVE_MM
57 .macro act_mm, rd
58 andn \rd, sp, #8128
59 andn \rd, \rd, #63
[all …]
/Linux-v5.4/arch/arm/mach-tegra/
Dsleep.h51 .macro cpu_to_halt_reg rd, rcpu
53 subne \rd, \rcpu, #1
54 movne \rd, \rd, lsl #3
55 addne \rd, \rd, #0x14
56 moveq \rd, #0
60 .macro cpu_to_csr_reg rd, rcpu
62 subne \rd, \rcpu, #1
63 movne \rd, \rd, lsl #3
64 addne \rd, \rd, #0x18
65 moveq \rd, #8
[all …]
/Linux-v5.4/arch/unicore32/kernel/
Ddebug-macro.S14 .macro put_word_ocd, rd, rx=r16
18 movc p1.c1, \rd, #1
26 .macro senduart, rd, rx
27 put_word_ocd \rd, \rx
30 .macro busyuart, rd, rx
33 .macro waituart, rd, rx
70 .macro senduart,rd,rx
71 str \rd, [\rx, #UART_THR_OFFSET]
74 .macro waituart,rd,rx
75 1001: ldr \rd, [\rx, #UART_LSR_OFFSET]
[all …]
/Linux-v5.4/arch/arm/lib/
Dio-writesb.S10 .macro outword, rd
12 strb \rd, [r0]
13 mov \rd, \rd, lsr #8
14 strb \rd, [r0]
15 mov \rd, \rd, lsr #8
16 strb \rd, [r0]
17 mov \rd, \rd, lsr #8
18 strb \rd, [r0]
20 mov lr, \rd, lsr #24
22 mov lr, \rd, lsr #16
[all …]
/Linux-v5.4/drivers/clk/samsung/
Dclk-exynos5-subcmu.c21 struct exynos5_subcmu_reg_dump *rd, in exynos5_subcmu_clk_save() argument
24 for (; num_regs > 0; --num_regs, ++rd) { in exynos5_subcmu_clk_save()
25 rd->save = readl(base + rd->offset); in exynos5_subcmu_clk_save()
26 writel((rd->save & ~rd->mask) | rd->value, base + rd->offset); in exynos5_subcmu_clk_save()
27 rd->save &= rd->mask; in exynos5_subcmu_clk_save()
32 struct exynos5_subcmu_reg_dump *rd, in exynos5_subcmu_clk_restore() argument
35 for (; num_regs > 0; --num_regs, ++rd) in exynos5_subcmu_clk_restore()
36 writel((readl(base + rd->offset) & ~rd->mask) | rd->save, in exynos5_subcmu_clk_restore()
37 base + rd->offset); in exynos5_subcmu_clk_restore()

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