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Searched refs:rb_cntl (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/radeon/
Dni_dma.c159 u32 rb_cntl; in cayman_dma_stop() local
166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
167 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
171 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
172 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
173 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
190 u32 rb_cntl, dma_cntl, ib_cntl; in cayman_dma_resume() local
211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
213 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in cayman_dma_resume()
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Dr600_dma.c101 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() local
106 rb_cntl &= ~DMA_RB_ENABLE; in r600_dma_stop()
107 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
123 u32 rb_cntl, dma_cntl, ib_cntl; in r600_dma_resume() local
132 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
134 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in r600_dma_resume()
136 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
149 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in r600_dma_resume()
170 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
Dcik_sdma.c252 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
264 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
265 rb_cntl &= ~SDMA_RB_ENABLE; in cik_sdma_gfx_stop()
266 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
368 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
389 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
391 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; in cik_sdma_gfx_resume()
393 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume()
406 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; in cik_sdma_gfx_resume()
415 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); in cik_sdma_gfx_resume()
Dni.c1689 uint32_t rb_cntl; in cayman_cp_resume() local
1694 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1695 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; in cayman_cp_resume()
1697 rb_cntl |= BUF_SWAP_32BIT; in cayman_cp_resume()
1699 WREG32(cp_rb_cntl[i], rb_cntl); in cayman_cp_resume()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dsdma_v2_4.c343 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_stop() local
351 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
352 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v2_4_gfx_stop()
353 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_stop()
413 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_resume() local
439 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
440 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
442 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v2_4_gfx_resume()
443 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v2_4_gfx_resume()
446 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_resume()
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Dsdma_v4_0.c809 u32 rb_cntl, ib_cntl; in sdma_v4_0_gfx_stop() local
820 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); in sdma_v4_0_gfx_stop()
821 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v4_0_gfx_stop()
822 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); in sdma_v4_0_gfx_stop()
853 u32 rb_cntl, ib_cntl; in sdma_v4_0_page_stop() local
866 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); in sdma_v4_0_page_stop()
867 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, in sdma_v4_0_page_stop()
869 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); in sdma_v4_0_page_stop()
960 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) in sdma_v4_0_rb_cntl() argument
965 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_0_rb_cntl()
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Dsdma_v3_0.c517 u32 rb_cntl, ib_cntl; in sdma_v3_0_gfx_stop() local
525 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
526 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v3_0_gfx_stop()
527 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_stop()
648 u32 rb_cntl, ib_cntl, wptr_poll_cntl; in sdma_v3_0_gfx_resume() local
677 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
678 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
680 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v3_0_gfx_resume()
681 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v3_0_gfx_resume()
684 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_resume()
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Dsi_dma.c115 u32 rb_cntl; in si_dma_stop() local
121 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
122 rb_cntl &= ~DMA_RB_ENABLE; in si_dma_stop()
123 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
134 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
146 rb_cntl = rb_bufsz << 1; in si_dma_start()
148 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in si_dma_start()
150 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
161 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in si_dma_start()
178 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); in si_dma_start()
Dsdma_v5_0.c483 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_stop() local
491 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop()
492 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_0_gfx_stop()
493 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop()
605 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_resume() local
623 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_resume()
624 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_0_gfx_resume()
626 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v5_0_gfx_resume()
627 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v5_0_gfx_resume()
630 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_resume()
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Dcik_sdma.c310 u32 rb_cntl; in cik_sdma_gfx_stop() local
318 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop()
319 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; in cik_sdma_gfx_stop()
320 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_stop()
435 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
463 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
465 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | in cik_sdma_gfx_resume()
468 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_resume()
482 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; in cik_sdma_gfx_resume()
492 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); in cik_sdma_gfx_resume()