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Searched refs:plls (Results 1 – 25 of 25) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/omapdrm/dss/
Dpll.c32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
50 dss->plls[i] = NULL; in dss_pll_unregister()
61 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_find()
62 if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0) in dss_pll_find()
63 return dss->plls[i]; in dss_pll_find()
Ddss.h255 struct dss_pll *plls[4]; member
/Linux-v5.4/sound/soc/uniphier/
Daio-cpu.c32 return chip->plls[pll_id].enable; in is_valid_pll()
138 pll = &aio->chip->plls[pll_id]; in find_divider()
640 chip->plls = devm_kcalloc(dev, in uniphier_aio_probe()
644 if (!chip->plls) in uniphier_aio_probe()
646 memcpy(chip->plls, chip->chip_spec->plls, in uniphier_aio_probe()
Daio.h220 const struct uniphier_aio_pll *plls; member
289 struct uniphier_aio_pll *plls; member
Daio-ld11.c378 .plls = uniphier_aio_pll_ld11,
388 .plls = uniphier_aio_pll_ld11,
Daio-pxs2.c294 .plls = uniphier_aio_pll_pxs2,
Daio-core.c146 chip->plls[pll_id].freq = freq; in aio_chip_set_pll()
548 switch (chip->plls[sub->aio->pll_out].freq) { in aio_port_set_clk()
573 switch (chip->plls[sub->aio->pll_out].freq) { in aio_port_set_clk()
/Linux-v5.4/drivers/clk/mediatek/
Dclk-mt8135.c613 static const struct mtk_pll_data plls[] = { variable
634 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in mtk_apmixedsys_init()
Dclk-mt7629.c337 static const struct mtk_pll_data plls[] = { variable
661 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), in mtk_apmixedsys_init()
Dclk-mt6797.c641 static const struct mtk_pll_data plls[] = { variable
673 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in mtk_apmixedsys_init()
Dclk-mt8516.c772 static const struct mtk_pll_data plls[] = { variable
801 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in mtk_apmixedsys_init()
Dclk-mt7622.c330 static const struct mtk_pll_data plls[] = { variable
680 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), in mtk_apmixedsys_init()
Dclk-mt6779.c1180 static const struct mtk_pll_data plls[] = { variable
1218 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt6779_apmixed_probe()
Dclk-pll.c345 const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) in mtk_clk_register_plls() argument
358 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_plls()
Dclk-mt8183.c1123 static const struct mtk_pll_data plls[] = { variable
1162 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8183_apmixed_probe()
Dclk-mt2712.c1224 static const struct mtk_pll_data plls[] = { variable
1268 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt2712_apmixed_probe()
Dclk-mt8173.c1061 static const struct mtk_pll_data plls[] = { variable
1097 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in mtk_apmixedsys_init()
Dclk-mtk.h239 const struct mtk_pll_data *plls, int num_plls,
/Linux-v5.4/arch/arm/plat-samsung/include/plat/
Dcpu-freq-core.h192 extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dactions,owl-cmu.txt28 The hosc clock used as input for the plls is generated outside the SoC. It is
Damlogic,axg-audio-clkc.txt18 * "mst_in[0-7]" - 8 input plls to generate clock signals
Dsamsung,s3c2410-clock.txt27 The xti clock used as input for the plls is generated outside the SoC. It is
/Linux-v5.4/drivers/cpufreq/
Ds3c24xx-cpufreq.c629 int s3c_plltab_register(struct cpufreq_frequency_table *plls, in s3c_plltab_register() argument
639 memcpy(vals, plls, size); in s3c_plltab_register()
/Linux-v5.4/drivers/clk/
Dclk-oxnas.c32 struct clk_oxnas_pll **plls; member
/Linux-v5.4/drivers/video/fbdev/intelfb/
Dintelfbhw.c53 static struct pll_min_max plls[PLLS_MAX] = { variable
663 return plls[index].ref_clk * m / n / p; in calc_vclock3()
669 struct pll_min_max *pll = &plls[index]; in calc_vclock()
885 struct pll_min_max *pll = &plls[index]; in splitm()
906 struct pll_min_max *pll = &plls[index]; in splitp()
945 struct pll_min_max *pll = &plls[index]; in calc_pll_params()