/Linux-v5.4/drivers/gpu/drm/omapdrm/dss/ |
D | pll.c | 32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register() 33 if (!dss->plls[i]) { in dss_pll_register() 34 dss->plls[i] = pll; in dss_pll_register() 48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister() 49 if (dss->plls[i] == pll) { in dss_pll_unregister() 50 dss->plls[i] = NULL; in dss_pll_unregister() 61 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_find() 62 if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0) in dss_pll_find() 63 return dss->plls[i]; in dss_pll_find()
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D | dss.h | 255 struct dss_pll *plls[4]; member
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/Linux-v5.4/sound/soc/uniphier/ |
D | aio-cpu.c | 32 return chip->plls[pll_id].enable; in is_valid_pll() 138 pll = &aio->chip->plls[pll_id]; in find_divider() 640 chip->plls = devm_kcalloc(dev, in uniphier_aio_probe() 644 if (!chip->plls) in uniphier_aio_probe() 646 memcpy(chip->plls, chip->chip_spec->plls, in uniphier_aio_probe()
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D | aio.h | 220 const struct uniphier_aio_pll *plls; member 289 struct uniphier_aio_pll *plls; member
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D | aio-ld11.c | 378 .plls = uniphier_aio_pll_ld11, 388 .plls = uniphier_aio_pll_ld11,
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D | aio-pxs2.c | 294 .plls = uniphier_aio_pll_pxs2,
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D | aio-core.c | 146 chip->plls[pll_id].freq = freq; in aio_chip_set_pll() 548 switch (chip->plls[sub->aio->pll_out].freq) { in aio_port_set_clk() 573 switch (chip->plls[sub->aio->pll_out].freq) { in aio_port_set_clk()
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/Linux-v5.4/drivers/clk/mediatek/ |
D | clk-mt8135.c | 613 static const struct mtk_pll_data plls[] = { variable 634 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in mtk_apmixedsys_init()
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D | clk-mt7629.c | 337 static const struct mtk_pll_data plls[] = { variable 661 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), in mtk_apmixedsys_init()
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D | clk-mt6797.c | 641 static const struct mtk_pll_data plls[] = { variable 673 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in mtk_apmixedsys_init()
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D | clk-mt8516.c | 772 static const struct mtk_pll_data plls[] = { variable 801 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in mtk_apmixedsys_init()
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D | clk-mt7622.c | 330 static const struct mtk_pll_data plls[] = { variable 680 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), in mtk_apmixedsys_init()
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D | clk-mt6779.c | 1180 static const struct mtk_pll_data plls[] = { variable 1218 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt6779_apmixed_probe()
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D | clk-pll.c | 345 const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) in mtk_clk_register_plls() argument 358 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_plls()
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D | clk-mt8183.c | 1123 static const struct mtk_pll_data plls[] = { variable 1162 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt8183_apmixed_probe()
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D | clk-mt2712.c | 1224 static const struct mtk_pll_data plls[] = { variable 1268 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in clk_mt2712_apmixed_probe()
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D | clk-mt8173.c | 1061 static const struct mtk_pll_data plls[] = { variable 1097 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); in mtk_apmixedsys_init()
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D | clk-mtk.h | 239 const struct mtk_pll_data *plls, int num_plls,
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/Linux-v5.4/arch/arm/plat-samsung/include/plat/ |
D | cpu-freq-core.h | 192 extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
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/Linux-v5.4/Documentation/devicetree/bindings/clock/ |
D | actions,owl-cmu.txt | 28 The hosc clock used as input for the plls is generated outside the SoC. It is
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D | amlogic,axg-audio-clkc.txt | 18 * "mst_in[0-7]" - 8 input plls to generate clock signals
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D | samsung,s3c2410-clock.txt | 27 The xti clock used as input for the plls is generated outside the SoC. It is
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/Linux-v5.4/drivers/cpufreq/ |
D | s3c24xx-cpufreq.c | 629 int s3c_plltab_register(struct cpufreq_frequency_table *plls, in s3c_plltab_register() argument 639 memcpy(vals, plls, size); in s3c_plltab_register()
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/Linux-v5.4/drivers/clk/ |
D | clk-oxnas.c | 32 struct clk_oxnas_pll **plls; member
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/Linux-v5.4/drivers/video/fbdev/intelfb/ |
D | intelfbhw.c | 53 static struct pll_min_max plls[PLLS_MAX] = { variable 663 return plls[index].ref_clk * m / n / p; in calc_vclock3() 669 struct pll_min_max *pll = &plls[index]; in calc_vclock() 885 struct pll_min_max *pll = &plls[index]; in splitm() 906 struct pll_min_max *pll = &plls[index]; in splitp() 945 struct pll_min_max *pll = &plls[index]; in calc_pll_params()
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