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Searched refs:pll_write_udelay (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_28nm.c119 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, in pll_28nm_software_reset()
121 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); in pll_28nm_software_reset()
332 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); in dsi_pll_28nm_enable_seq_hpm()
335 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); in dsi_pll_28nm_enable_seq_hpm()
338 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in dsi_pll_28nm_enable_seq_hpm()
341 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); in dsi_pll_28nm_enable_seq_hpm()
345 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, in dsi_pll_28nm_enable_seq_hpm()
362 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); in dsi_pll_28nm_enable_seq_hpm()
365 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); in dsi_pll_28nm_enable_seq_hpm()
368 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); in dsi_pll_28nm_enable_seq_hpm()
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Ddsi_pll.h52 static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us) in pll_write_udelay() function
Ddsi_pll_14nm.c499 pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); in pll_14nm_software_reset()