Searched refs:pll_mode (Results 1 – 10 of 10) sorted by relevance
42 u32 pll_mode, pll_m, pll_n; in of_artpec6_clkctrl_setup() local65 pll_mode = (readl(clkdata->syscon_base) >> 6) & 3; in of_artpec6_clkctrl_setup()66 switch (pll_mode) { in of_artpec6_clkctrl_setup()
31 enum pll_mode { enum46 static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw) in zynqmp_pll_get_mode()
66 enum pll_mode { enum105 static inline enum pll_mode pll_frac_get_mode(struct clk_hw *hw) in pll_frac_get_mode()114 static inline void pll_frac_set_mode(struct clk_hw *hw, enum pll_mode mode) in pll_frac_set_mode()
223 u8 pll_mode; member
291 common->w9116_features.pll_mode = 0x0; in rsi_set_default_parameters()1684 w9116_features->pll_mode = common->w9116_features.pll_mode; in rsi_send_w9116_features()
673 u8 pll_mode; member
582 u8 pll_mode; member750 pll_ratio_table[i].pll_mode in cs42l42_pll_config()
184 u8 pll_mode; member277 pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT); in cs43130_pll_config()
680 u32 pll_mode : 1; member
1243 w100_pwr_state.pll_cntl.f.pll_mode = 0x0; /* uses VCO clock */ in w100_pwm_setup()
