Searched refs:pll_in_use (Results 1 – 6 of 6) sorted by relevance
1740 u32 pll_in_use = 0; in radeon_get_pll_use_mask() local1748 pll_in_use |= (1 << test_radeon_crtc->pll_id); in radeon_get_pll_use_mask()1750 return pll_in_use; in radeon_get_pll_use_mask()1882 u32 pll_in_use; in radeon_atom_pick_pll() local1906 pll_in_use = radeon_get_pll_use_mask(crtc); in radeon_atom_pick_pll()1907 if (!(pll_in_use & (1 << ATOM_PPLL2))) in radeon_atom_pick_pll()1909 if (!(pll_in_use & (1 << ATOM_PPLL1))) in radeon_atom_pick_pll()1915 pll_in_use = radeon_get_pll_use_mask(crtc); in radeon_atom_pick_pll()1916 if (!(pll_in_use & (1 << ATOM_PPLL2))) in radeon_atom_pick_pll()1918 if (!(pll_in_use & (1 << ATOM_PPLL1))) in radeon_atom_pick_pll()[all …]
265 u32 pll_in_use = 0; in amdgpu_pll_get_use_mask() local273 pll_in_use |= (1 << test_amdgpu_crtc->pll_id); in amdgpu_pll_get_use_mask()275 return pll_in_use; in amdgpu_pll_get_use_mask()
2126 u32 pll_in_use; in dce_v8_0_pick_pll() local2149 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v8_0_pick_pll()2150 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v8_0_pick_pll()2152 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v8_0_pick_pll()2158 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v8_0_pick_pll()2159 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v8_0_pick_pll()2161 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v8_0_pick_pll()2163 if (!(pll_in_use & (1 << ATOM_PPLL0))) in dce_v8_0_pick_pll()
2269 u32 pll_in_use; in dce_v11_0_pick_pll() local2326 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v11_0_pick_pll()2328 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v11_0_pick_pll()2330 if (!(pll_in_use & (1 << ATOM_PPLL0))) in dce_v11_0_pick_pll()2335 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v11_0_pick_pll()2337 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v11_0_pick_pll()2339 if (!(pll_in_use & (1 << ATOM_PPLL0))) in dce_v11_0_pick_pll()
2236 u32 pll_in_use; in dce_v10_0_pick_pll() local2257 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v10_0_pick_pll()2258 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v10_0_pick_pll()2260 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v10_0_pick_pll()2262 if (!(pll_in_use & (1 << ATOM_PPLL0))) in dce_v10_0_pick_pll()
2132 u32 pll_in_use; in dce_v6_0_pick_pll() local2149 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v6_0_pick_pll()2150 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v6_0_pick_pll()2152 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v6_0_pick_pll()
