| /Linux-v5.4/Documentation/devicetree/bindings/clock/ |
| D | renesas,sh73a0-cpg-clocks.txt | 19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
32 "pll3", "dsi0phy", "dsi1phy",
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| D | renesas,rcar-gen2-cpg-clocks.txt | 24 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
45 clock-output-names = "main", "pll0, "pll1", "pll3",
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| D | prima2-clock.txt | 19 pll3 4
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| D | sunxi.txt | 13 "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
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| /Linux-v5.4/drivers/clk/sunxi/ |
| D | Makefile | 18 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-pll3.o
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| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| D | intel_dpll_mgr.c | 1562 temp |= pll->state.hw_state.pll3; in bxt_ddi_pll_enable()
1686 hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
1687 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
1846 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_set_dpll_hw_state()
1930 hw_state->pll3, in bxt_dump_hw_state()
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| D | intel_ddi.c | 1660 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) in bxt_calc_pll_link()
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| D | intel_display.c | 12810 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); in intel_pipe_config_compare()
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| /Linux-v5.4/drivers/clk/sirf/ |
| D | clk-atlas6.c | 61 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
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| D | clk-prima2.c | 60 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
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| /Linux-v5.4/drivers/gpu/drm/tegra/ |
| D | sor.c | 367 unsigned int pll3; member
1732 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1734 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_edp_enable()
2462 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2464 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2664 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2673 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
3041 .pll3 = 0x1a,
3066 .pll3 = 0x1a,
3110 .pll3 = 0x166,
[all …]
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| /Linux-v5.4/drivers/clk/qcom/ |
| D | gcc-msm8960.c | 28 static struct clk_pll pll3 = { variable
3142 [PLL3] = &pll3.clkr,
3370 [PLL3] = &pll3.clkr,
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| D | gcc-ipq806x.c | 55 static struct clk_pll pll3 = { variable
2756 [PLL3] = &pll3.clkr,
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | sh73a0.dtsi | 638 "pll3", "dsi0phy", "dsi1phy",
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