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/Linux-v5.4/drivers/gpu/drm/xen/
Dxen_drm_front_kms.c98 static void send_pending_event(struct xen_drm_front_drm_pipeline *pipeline) in send_pending_event() argument
100 struct drm_crtc *crtc = &pipeline->pipe.crtc; in send_pending_event()
105 if (pipeline->pending_event) in send_pending_event()
106 drm_crtc_send_vblank_event(crtc, pipeline->pending_event); in send_pending_event()
107 pipeline->pending_event = NULL; in send_pending_event()
115 struct xen_drm_front_drm_pipeline *pipeline = in display_enable() local
124 ret = xen_drm_front_mode_set(pipeline, crtc->x, crtc->y, in display_enable()
131 pipeline->conn_connected = false; in display_enable()
139 struct xen_drm_front_drm_pipeline *pipeline = in display_disable() local
144 ret = xen_drm_front_mode_set(pipeline, 0, 0, 0, 0, 0, in display_disable()
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Dxen_drm_front_conn.c48 struct xen_drm_front_drm_pipeline *pipeline = in connector_detect() local
52 pipeline->conn_connected = false; in connector_detect()
54 return pipeline->conn_connected ? connector_status_connected : in connector_detect()
62 struct xen_drm_front_drm_pipeline *pipeline = in connector_get_modes() local
73 videomode.hactive = pipeline->width; in connector_get_modes()
74 videomode.vactive = pipeline->height; in connector_get_modes()
103 struct xen_drm_front_drm_pipeline *pipeline = in xen_drm_front_conn_init() local
108 pipeline->conn_connected = true; in xen_drm_front_conn_init()
Dxen_drm_front.h129 struct xen_drm_front_drm_pipeline pipeline[XEN_DRM_FRONT_MAX_CRTCS]; member
142 int xen_drm_front_mode_set(struct xen_drm_front_drm_pipeline *pipeline,
Dxen_drm_front_kms.h23 void xen_drm_front_kms_on_frame_done(struct xen_drm_front_drm_pipeline *pipeline,
/Linux-v5.4/drivers/isdn/mISDN/
Ddsp_pipeline.c177 int dsp_pipeline_init(struct dsp_pipeline *pipeline) in dsp_pipeline_init() argument
179 if (!pipeline) in dsp_pipeline_init()
182 INIT_LIST_HEAD(&pipeline->list); in dsp_pipeline_init()
191 static inline void _dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in _dsp_pipeline_destroy() argument
195 list_for_each_entry_safe(entry, n, &pipeline->list, list) { in _dsp_pipeline_destroy()
198 dsp_hwec_disable(container_of(pipeline, struct dsp, in _dsp_pipeline_destroy()
199 pipeline)); in _dsp_pipeline_destroy()
206 void dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in dsp_pipeline_destroy() argument
209 if (!pipeline) in dsp_pipeline_destroy()
212 _dsp_pipeline_destroy(pipeline); in dsp_pipeline_destroy()
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Ddsp.h236 pipeline; member
271 extern int dsp_pipeline_init(struct dsp_pipeline *pipeline);
272 extern void dsp_pipeline_destroy(struct dsp_pipeline *pipeline);
273 extern int dsp_pipeline_build(struct dsp_pipeline *pipeline, const char *cfg);
274 extern void dsp_pipeline_process_tx(struct dsp_pipeline *pipeline, u8 *data,
276 extern void dsp_pipeline_process_rx(struct dsp_pipeline *pipeline, u8 *data,
/Linux-v5.4/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_crtc.c91 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in crtc_flush() local
98 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
123 mixer = mdp5_cstate->pipeline.mixer; in crtc_flush_all()
126 r_mixer = mdp5_cstate->pipeline.r_mixer; in crtc_flush_all()
137 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in complete_flip() local
155 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); in complete_flip()
214 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in blend_setup() local
220 struct mdp5_hw_mixer *mixer = pipeline->mixer; in blend_setup()
222 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; in blend_setup()
356 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, in blend_setup()
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Dmdp5_ctl.c135 static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in set_ctl_op() argument
138 struct mdp5_interface *intf = pipeline->intf; in set_ctl_op()
159 if (pipeline->r_mixer) in set_ctl_op()
168 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in mdp5_ctl_set_pipeline() argument
171 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_pipeline()
177 set_ctl_op(ctl, pipeline); in mdp5_ctl_set_pipeline()
183 struct mdp5_pipeline *pipeline) in start_signal_needed() argument
185 struct mdp5_interface *intf = pipeline->intf; in start_signal_needed()
225 struct mdp5_pipeline *pipeline, in mdp5_ctl_set_encoder_state() argument
228 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_encoder_state()
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Dmdp5_cmd_encoder.c139 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_disable() local
146 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_cmd_encoder_disable()
147 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_disable()
159 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_enable() local
168 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_enable()
170 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_cmd_encoder_enable()
Dmdp5_ctl.h37 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
55 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
72 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
Dmdp5_encoder.c199 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_disable() local
208 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_vid_encoder_disable()
213 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_disable()
236 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_enable() local
247 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_enable()
249 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_vid_encoder_enable()
303 mdp5_cstate->pipeline.intf = intf; in mdp5_encoder_atomic_check()
/Linux-v5.4/drivers/net/wireless/ti/wl18xx/
Ddebugfs.c143 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, hs_tx_stat_fifo_int, "%u");
144 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_tx_stat_fifo_int, "%u");
145 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_rx_stat_fifo_int, "%u");
146 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, rx_complete_stat_fifo_int, "%u");
147 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_proc_swi, "%u");
148 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, post_proc_swi, "%u");
149 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, sec_frag_swi, "%u");
150 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_to_defrag_swi, "%u");
151 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, defrag_to_rx_xfer_swi, "%u");
152 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, dec_packet_in, "%u");
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/Linux-v5.4/Documentation/gpu/
Dkomeda-kms.rst15 architecture. A display pipeline is made up of multiple individual and
16 functional pipeline stages called components, and every component has some
17 specific capabilities that can give the flowed pipeline pixel data a
24 Layer is the first pipeline stage, which prepares the pixel data for the next
58 Final stage of display pipeline, Timing controller is not for the pixel
94 Single pipeline data flow
98 :alt: Single pipeline digraph
99 :caption: Single pipeline data flow
140 Dual pipeline with Slave enabled
144 :alt: Slave pipeline digraph
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/Linux-v5.4/Documentation/devicetree/bindings/display/
Darm,komeda.txt18 Required properties for sub-node: pipeline@nq
19 Each device contains one or two pipeline sub-nodes (at least one), each
20 pipeline node should provide properties:
21 - reg: Zero-indexed identifier for the pipeline
27 - port: each pipeline connect to an encoder input port. The connection is
53 dp0_pipe0: pipeline@0 {
65 dp0_pipe1: pipeline@1 {
/Linux-v5.4/tools/testing/selftests/kvm/lib/
Dassert.c33 const char *pipeline = "|cat -n 1>&2"; in test_dump_stack() local
34 char cmd[strlen(addr2line) + strlen(pipeline) + in test_dump_stack()
51 c += sprintf(c, "%s", pipeline); in test_dump_stack()
/Linux-v5.4/sound/soc/sof/
Dtopology.c1364 struct sof_ipc_pipe_new *pipeline, in sof_load_pipeline_ipc() argument
1370 ret = sof_ipc_tx_message(sdev->ipc, pipeline->hdr.cmd, pipeline, in sof_load_pipeline_ipc()
1371 sizeof(*pipeline), r, sizeof(*r)); in sof_load_pipeline_ipc()
1378 ret = snd_sof_dsp_core_power_up(sdev, 1 << pipeline->core); in sof_load_pipeline_ipc()
1381 pipeline->core); in sof_load_pipeline_ipc()
1386 sdev->enabled_cores_mask |= 1 << pipeline->core; in sof_load_pipeline_ipc()
1416 struct sof_ipc_pipe_new *pipeline; in sof_widget_load_pipeline() local
1420 pipeline = kzalloc(sizeof(*pipeline), GFP_KERNEL); in sof_widget_load_pipeline()
1421 if (!pipeline) in sof_widget_load_pipeline()
1425 pipeline->hdr.size = sizeof(*pipeline); in sof_widget_load_pipeline()
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/Linux-v5.4/Documentation/media/v4l-drivers/
Dqcom_camss.rst38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
40 interface feeds the input data to the image processing pipeline. The image
41 processing pipeline contains also a scale and crop module at the end. Three
43 pipeline. The VFE also contains the AXI bus interface which writes the output
137 The media controller pipeline graph is as follows (with connected two / three
146 Media pipeline graph 8x16
152 Media pipeline graph 8x96
Dvimc.rst18 :alt: Diagram of the default media pipeline topology
21 Media pipeline graph on vimc
28 configuration on each linked subdevice to stream frames through the pipeline.
/Linux-v5.4/Documentation/media/uapi/v4l/
Ddev-subdev.rst97 responsible for configuring every block in the video pipeline according
98 to the requested format at the pipeline input and/or output.
101 image sizes at the output of a pipeline can be achieved using different
103 :ref:`pipeline-scaling`, where image scaling can be performed on both
109 .. kernel-figure:: pipeline.dot
110 :alt: pipeline.dot
115 High quality and high speed pipeline configuration
121 Depending on the use case (quality vs. speed), the pipeline must be
123 every point in the pipeline explicitly.
133 whole pipeline and making sure that connected pads have compatible
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/Linux-v5.4/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,video.txt7 Xilinx video IP pipeline processes video streams through one or more Xilinx
10 node of the VIPP represents as a top level node of the pipeline and defines
Dvideo.txt6 creating a video pipeline.
12 The whole pipeline is represented by an AMBA bus child node in the device
/Linux-v5.4/drivers/gpu/drm/arm/display/komeda/
Dkomeda_pipeline.c154 return komeda_pipeline_get_first_component(c->pipeline, avail_inputs); in komeda_component_pickup_input()
203 c->pipeline = pipe; in komeda_component_add()
269 struct komeda_pipeline *pipe = c->pipeline; in komeda_component_verify_inputs()
334 return slave ? slave->pipeline : NULL; in komeda_pipeline_get_slave()
/Linux-v5.4/drivers/gpu/drm/sun4i/
Dsun4i_drv.c359 struct device_node *pipeline = of_parse_phandle(np, in sun4i_drv_probe() local
362 if (!pipeline) in sun4i_drv_probe()
365 kfifo_put(&list.fifo, pipeline); in sun4i_drv_probe()
/Linux-v5.4/Documentation/media/
D.gitignore5 uapi/v4l/pipeline.svg
/Linux-v5.4/Documentation/devicetree/bindings/display/bridge/
Dmegachips-stdpxxxx-ge-b850v3-fw.txt5 The video processing pipeline on the second output on the GE B850v3:
15 The hardware do not provide control over the video processing pipeline, as the

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