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Searched refs:phys_enc (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder_phys_cmd.c38 static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_cmd_is_master() argument
40 return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false; in dpu_encoder_phys_cmd_is_master()
44 struct dpu_encoder_phys *phys_enc, in dpu_encoder_phys_cmd_mode_fixup() argument
48 if (phys_enc) in dpu_encoder_phys_cmd_mode_fixup()
49 DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n"); in dpu_encoder_phys_cmd_mode_fixup()
54 struct dpu_encoder_phys *phys_enc) in _dpu_encoder_phys_cmd_update_intf_cfg() argument
57 to_dpu_encoder_phys_cmd(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
61 if (!phys_enc) in _dpu_encoder_phys_cmd_update_intf_cfg()
64 ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_cmd_update_intf_cfg()
68 intf_cfg.intf = phys_enc->intf_idx; in _dpu_encoder_phys_cmd_update_intf_cfg()
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Ddpu_encoder_phys_vid.c28 struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_vid_is_master() argument
32 if (phys_enc->split_role != ENC_ROLE_SLAVE) in dpu_encoder_phys_vid_is_master()
39 const struct dpu_encoder_phys *phys_enc, in drm_mode_to_intf_timing_params() argument
87 if (phys_enc->hw_intf->cap->type == INTF_DSI) { in drm_mode_to_intf_timing_params()
138 struct dpu_encoder_phys *phys_enc, in programmable_fetch_get_num_lines() argument
142 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; in programmable_fetch_get_num_lines()
150 DPU_DEBUG_VIDENC(phys_enc, in programmable_fetch_get_num_lines()
157 DPU_DEBUG_VIDENC(phys_enc, in programmable_fetch_get_num_lines()
161 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n"); in programmable_fetch_get_num_lines()
165 DPU_DEBUG_VIDENC(phys_enc, in programmable_fetch_get_num_lines()
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Ddpu_encoder_phys.h135 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
136 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
137 int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
138 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
139 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
140 void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
141 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
143 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
319 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
322 struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_get_3d_blend_mode() argument
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Ddpu_encoder.c212 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_report_irq_timeout() argument
216 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, in dpu_encoder_helper_report_irq_timeout()
217 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); in dpu_encoder_helper_report_irq_timeout()
219 if (phys_enc->parent_ops->handle_frame_done) in dpu_encoder_helper_report_irq_timeout()
220 phys_enc->parent_ops->handle_frame_done( in dpu_encoder_helper_report_irq_timeout()
221 phys_enc->parent, phys_enc, in dpu_encoder_helper_report_irq_timeout()
228 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_wait_for_irq() argument
236 if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) { in dpu_encoder_helper_wait_for_irq()
240 irq = &phys_enc->irq[intr_idx]; in dpu_encoder_helper_wait_for_irq()
245 if (phys_enc->enable_state == DPU_ENC_DISABLED) { in dpu_encoder_helper_wait_for_irq()
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