Searched refs:phy_ctl (Results 1 – 5 of 5) sorted by relevance
254 u16 phy_ctl = 0; in b43_generate_txhdr() local371 phy_ctl |= B43_TXH_PHY_ENC_OFDM; in b43_generate_txhdr()373 phy_ctl |= B43_TXH_PHY_ENC_CCK; in b43_generate_txhdr()375 phy_ctl |= B43_TXH_PHY_SHORTPRMBL; in b43_generate_txhdr()379 phy_ctl |= B43_TXH_PHY_ANT01AUTO; in b43_generate_txhdr()382 phy_ctl |= B43_TXH_PHY_ANT0; in b43_generate_txhdr()385 phy_ctl |= B43_TXH_PHY_ANT1; in b43_generate_txhdr()388 phy_ctl |= B43_TXH_PHY_ANT2; in b43_generate_txhdr()391 phy_ctl |= B43_TXH_PHY_ANT3; in b43_generate_txhdr()564 txhdr->phy_ctl = cpu_to_le16(phy_ctl); in b43_generate_txhdr()
29 __le16 phy_ctl; /* PHY TX control */ member
189 u16 phy_ctl = 0; in generate_txhdr_fw3() local264 phy_ctl |= B43legacy_TX4_PHY_ENC_OFDM; in generate_txhdr_fw3()266 phy_ctl |= B43legacy_TX4_PHY_SHORTPRMBL; in generate_txhdr_fw3()267 phy_ctl |= B43legacy_TX4_PHY_ANTLAST; in generate_txhdr_fw3()340 txhdr->phy_ctl = cpu_to_le16(phy_ctl); in generate_txhdr_fw3()
203 u32 phy_ctl; in pcie_phy_read() local211 phy_ctl = PCIE_PHY_CTRL_RD; in pcie_phy_read()212 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); in pcie_phy_read()
