Searched refs:num_wm_dmif_sets (Results 1 – 5 of 5) sorted by relevance
554 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; in pp_rv_set_wm_ranges()557 for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { in pp_rv_set_wm_ranges()676 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; in pp_nv_set_wm_ranges()679 for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { in pp_nv_set_wm_ranges()
174 uint32_t num_wm_dmif_sets; member
713 if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || wm_with_clock_ranges->num_wm_mcif_sets > 4) in smu_set_watermarks_for_clocks_ranges()716 for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) { in smu_set_watermarks_for_clocks_ranges()
1300 if (clock_ranges->num_wm_dmif_sets > 4 || in navi10_set_watermarks_table()1304 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { in navi10_set_watermarks_table()
3068 if (clock_ranges->num_wm_dmif_sets > 4 || in vega20_set_watermarks_table()3072 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { in vega20_set_watermarks_table()
