Searched refs:num_tile_mode_states (Results 1 – 5 of 5) sorted by relevance
399 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v6_0_tiling_mode_table_init() local640 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()846 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()1070 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()1294 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
2128 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init() local2135 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2303 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2495 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2684 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2887 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3089 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3258 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3435 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
1025 const u32 num_tile_mode_states = in gfx_v7_0_tiling_mode_table_init() local1048 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1215 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1398 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1568 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
2337 const u32 num_tile_mode_states = in cik_tiling_mode_table_init() local2363 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2506 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2649 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2874 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()3017 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2496 const u32 num_tile_mode_states = in si_tiling_mode_table_init() local2513 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()2727 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()2942 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
