Searched refs:num_compute_rings (Results 1 – 9 of 9) sorted by relevance
223 adev->gfx.num_compute_rings = in amdgpu_gfx_compute_queue_acquire()228 if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS)) in amdgpu_gfx_compute_queue_acquire()229 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in amdgpu_gfx_compute_queue_acquire()414 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in amdgpu_gfx_mqd_sw_init()450 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in amdgpu_gfx_mqd_sw_fini()477 adev->gfx.num_compute_rings)) in amdgpu_gfx_disable_kcq()480 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_gfx_disable_kcq()516 adev->gfx.num_compute_rings + in amdgpu_gfx_enable_kcq()524 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_gfx_enable_kcq()
135 for (j = 0; j < adev->gfx.num_compute_rings; ++j) in amdgpu_ctx_init()137 num_rings = adev->gfx.num_compute_rings; in amdgpu_ctx_init()
1373 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; in gfx_v8_0_mec_init()2102 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()4353 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_cp_compute_enable()4396 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); in gfx_v8_0_kiq_kcq_enable()4410 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()4747 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()4790 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()4858 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); in gfx_v8_0_kcq_disable()4862 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()5063 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()[all …]
296 unsigned num_compute_rings; member
1737 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; in gfx_v9_0_mec_init()2357 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_sw_fini()3280 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_cp_compute_enable()3365 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8); in gfx_v9_0_kiq_kcq_enable()3381 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kiq_kcq_enable()3801 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kcq_resume()3865 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_cp_resume()3918 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); in gfx_v9_0_kcq_disable()3922 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kcq_disable()4405 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v9_0_early_init()[all …]
2709 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_cp_compute_enable()2788 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()3129 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()3139 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()4232 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v7_0_early_init()4531 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()4880 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()4905 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_fault()5065 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
1065 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; in gfx_v10_0_mec_init()1468 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_sw_fini()2886 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_cp_compute_enable()3555 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_kcq_resume()3625 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_cp_resume()3981 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v10_0_early_init()4972 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_eop_irq()5044 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_handle_priv_fault()5280 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_set_ring_funcs()
1964 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_cp_gfx_enable()3072 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS; in gfx_v6_0_early_init()3123 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v6_0_sw_init()3155 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_sw_fini()3542 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_set_ring_funcs()
326 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_hw_ip_info()
