1 /**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 #include <linux/pci.h>
19 #include <linux/netdevice.h>
20 #include <linux/vmalloc.h>
21 #include "liquidio_common.h"
22 #include "octeon_droq.h"
23 #include "octeon_iq.h"
24 #include "response_manager.h"
25 #include "octeon_device.h"
26 #include "octeon_main.h"
27 #include "octeon_network.h"
28 #include "cn66xx_regs.h"
29 #include "cn66xx_device.h"
30 #include "cn23xx_pf_device.h"
31 #include "cn23xx_vf_device.h"
32
33 struct niclist {
34 struct list_head list;
35 void *ptr;
36 };
37
38 struct __dispatch {
39 struct list_head list;
40 struct octeon_recv_info *rinfo;
41 octeon_dispatch_fn_t disp_fn;
42 };
43
44 /** Get the argument that the user set when registering dispatch
45 * function for a given opcode/subcode.
46 * @param octeon_dev - the octeon device pointer.
47 * @param opcode - the opcode for which the dispatch argument
48 * is to be checked.
49 * @param subcode - the subcode for which the dispatch argument
50 * is to be checked.
51 * @return Success: void * (argument to the dispatch function)
52 * @return Failure: NULL
53 *
54 */
octeon_get_dispatch_arg(struct octeon_device * octeon_dev,u16 opcode,u16 subcode)55 void *octeon_get_dispatch_arg(struct octeon_device *octeon_dev,
56 u16 opcode, u16 subcode)
57 {
58 int idx;
59 struct list_head *dispatch;
60 void *fn_arg = NULL;
61 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
62
63 idx = combined_opcode & OCTEON_OPCODE_MASK;
64
65 spin_lock_bh(&octeon_dev->dispatch.lock);
66
67 if (octeon_dev->dispatch.count == 0) {
68 spin_unlock_bh(&octeon_dev->dispatch.lock);
69 return NULL;
70 }
71
72 if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) {
73 fn_arg = octeon_dev->dispatch.dlist[idx].arg;
74 } else {
75 list_for_each(dispatch,
76 &octeon_dev->dispatch.dlist[idx].list) {
77 if (((struct octeon_dispatch *)dispatch)->opcode ==
78 combined_opcode) {
79 fn_arg = ((struct octeon_dispatch *)
80 dispatch)->arg;
81 break;
82 }
83 }
84 }
85
86 spin_unlock_bh(&octeon_dev->dispatch.lock);
87 return fn_arg;
88 }
89
90 /** Check for packets on Droq. This function should be called with lock held.
91 * @param droq - Droq on which count is checked.
92 * @return Returns packet count.
93 */
octeon_droq_check_hw_for_pkts(struct octeon_droq * droq)94 u32 octeon_droq_check_hw_for_pkts(struct octeon_droq *droq)
95 {
96 u32 pkt_count = 0;
97 u32 last_count;
98
99 pkt_count = readl(droq->pkts_sent_reg);
100
101 last_count = pkt_count - droq->pkt_count;
102 droq->pkt_count = pkt_count;
103
104 /* we shall write to cnts at napi irq enable or end of droq tasklet */
105 if (last_count)
106 atomic_add(last_count, &droq->pkts_pending);
107
108 return last_count;
109 }
110
octeon_droq_compute_max_packet_bufs(struct octeon_droq * droq)111 static void octeon_droq_compute_max_packet_bufs(struct octeon_droq *droq)
112 {
113 u32 count = 0;
114
115 /* max_empty_descs is the max. no. of descs that can have no buffers.
116 * If the empty desc count goes beyond this value, we cannot safely
117 * read in a 64K packet sent by Octeon
118 * (64K is max pkt size from Octeon)
119 */
120 droq->max_empty_descs = 0;
121
122 do {
123 droq->max_empty_descs++;
124 count += droq->buffer_size;
125 } while (count < (64 * 1024));
126
127 droq->max_empty_descs = droq->max_count - droq->max_empty_descs;
128 }
129
octeon_droq_reset_indices(struct octeon_droq * droq)130 static void octeon_droq_reset_indices(struct octeon_droq *droq)
131 {
132 droq->read_idx = 0;
133 droq->write_idx = 0;
134 droq->refill_idx = 0;
135 droq->refill_count = 0;
136 atomic_set(&droq->pkts_pending, 0);
137 }
138
139 static void
octeon_droq_destroy_ring_buffers(struct octeon_device * oct,struct octeon_droq * droq)140 octeon_droq_destroy_ring_buffers(struct octeon_device *oct,
141 struct octeon_droq *droq)
142 {
143 u32 i;
144 struct octeon_skb_page_info *pg_info;
145
146 for (i = 0; i < droq->max_count; i++) {
147 pg_info = &droq->recv_buf_list[i].pg_info;
148 if (!pg_info)
149 continue;
150
151 if (pg_info->dma)
152 lio_unmap_ring(oct->pci_dev,
153 (u64)pg_info->dma);
154 pg_info->dma = 0;
155
156 if (pg_info->page)
157 recv_buffer_destroy(droq->recv_buf_list[i].buffer,
158 pg_info);
159
160 droq->recv_buf_list[i].buffer = NULL;
161 }
162
163 octeon_droq_reset_indices(droq);
164 }
165
166 static int
octeon_droq_setup_ring_buffers(struct octeon_device * oct,struct octeon_droq * droq)167 octeon_droq_setup_ring_buffers(struct octeon_device *oct,
168 struct octeon_droq *droq)
169 {
170 u32 i;
171 void *buf;
172 struct octeon_droq_desc *desc_ring = droq->desc_ring;
173
174 for (i = 0; i < droq->max_count; i++) {
175 buf = recv_buffer_alloc(oct, &droq->recv_buf_list[i].pg_info);
176
177 if (!buf) {
178 dev_err(&oct->pci_dev->dev, "%s buffer alloc failed\n",
179 __func__);
180 droq->stats.rx_alloc_failure++;
181 return -ENOMEM;
182 }
183
184 droq->recv_buf_list[i].buffer = buf;
185 droq->recv_buf_list[i].data = get_rbd(buf);
186 desc_ring[i].info_ptr = 0;
187 desc_ring[i].buffer_ptr =
188 lio_map_ring(droq->recv_buf_list[i].buffer);
189 }
190
191 octeon_droq_reset_indices(droq);
192
193 octeon_droq_compute_max_packet_bufs(droq);
194
195 return 0;
196 }
197
octeon_delete_droq(struct octeon_device * oct,u32 q_no)198 int octeon_delete_droq(struct octeon_device *oct, u32 q_no)
199 {
200 struct octeon_droq *droq = oct->droq[q_no];
201
202 dev_dbg(&oct->pci_dev->dev, "%s[%d]\n", __func__, q_no);
203
204 octeon_droq_destroy_ring_buffers(oct, droq);
205 vfree(droq->recv_buf_list);
206
207 if (droq->desc_ring)
208 lio_dma_free(oct, (droq->max_count * OCT_DROQ_DESC_SIZE),
209 droq->desc_ring, droq->desc_ring_dma);
210
211 memset(droq, 0, OCT_DROQ_SIZE);
212 oct->io_qmask.oq &= ~(1ULL << q_no);
213 vfree(oct->droq[q_no]);
214 oct->droq[q_no] = NULL;
215 oct->num_oqs--;
216
217 return 0;
218 }
219
octeon_init_droq(struct octeon_device * oct,u32 q_no,u32 num_descs,u32 desc_size,void * app_ctx)220 int octeon_init_droq(struct octeon_device *oct,
221 u32 q_no,
222 u32 num_descs,
223 u32 desc_size,
224 void *app_ctx)
225 {
226 struct octeon_droq *droq;
227 u32 desc_ring_size = 0, c_num_descs = 0, c_buf_size = 0;
228 u32 c_pkts_per_intr = 0, c_refill_threshold = 0;
229 int numa_node = dev_to_node(&oct->pci_dev->dev);
230
231 dev_dbg(&oct->pci_dev->dev, "%s[%d]\n", __func__, q_no);
232
233 droq = oct->droq[q_no];
234 memset(droq, 0, OCT_DROQ_SIZE);
235
236 droq->oct_dev = oct;
237 droq->q_no = q_no;
238 if (app_ctx)
239 droq->app_ctx = app_ctx;
240 else
241 droq->app_ctx = (void *)(size_t)q_no;
242
243 c_num_descs = num_descs;
244 c_buf_size = desc_size;
245 if (OCTEON_CN6XXX(oct)) {
246 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx);
247
248 c_pkts_per_intr = (u32)CFG_GET_OQ_PKTS_PER_INTR(conf6x);
249 c_refill_threshold =
250 (u32)CFG_GET_OQ_REFILL_THRESHOLD(conf6x);
251 } else if (OCTEON_CN23XX_PF(oct)) {
252 struct octeon_config *conf23 = CHIP_CONF(oct, cn23xx_pf);
253
254 c_pkts_per_intr = (u32)CFG_GET_OQ_PKTS_PER_INTR(conf23);
255 c_refill_threshold = (u32)CFG_GET_OQ_REFILL_THRESHOLD(conf23);
256 } else if (OCTEON_CN23XX_VF(oct)) {
257 struct octeon_config *conf23 = CHIP_CONF(oct, cn23xx_vf);
258
259 c_pkts_per_intr = (u32)CFG_GET_OQ_PKTS_PER_INTR(conf23);
260 c_refill_threshold = (u32)CFG_GET_OQ_REFILL_THRESHOLD(conf23);
261 } else {
262 return 1;
263 }
264
265 droq->max_count = c_num_descs;
266 droq->buffer_size = c_buf_size;
267
268 desc_ring_size = droq->max_count * OCT_DROQ_DESC_SIZE;
269 droq->desc_ring = lio_dma_alloc(oct, desc_ring_size,
270 (dma_addr_t *)&droq->desc_ring_dma);
271
272 if (!droq->desc_ring) {
273 dev_err(&oct->pci_dev->dev,
274 "Output queue %d ring alloc failed\n", q_no);
275 return 1;
276 }
277
278 dev_dbg(&oct->pci_dev->dev, "droq[%d]: desc_ring: virt: 0x%p, dma: %lx\n",
279 q_no, droq->desc_ring, droq->desc_ring_dma);
280 dev_dbg(&oct->pci_dev->dev, "droq[%d]: num_desc: %d\n", q_no,
281 droq->max_count);
282
283 droq->recv_buf_list = (struct octeon_recv_buffer *)
284 vzalloc_node(array_size(droq->max_count, OCT_DROQ_RECVBUF_SIZE),
285 numa_node);
286 if (!droq->recv_buf_list)
287 droq->recv_buf_list = (struct octeon_recv_buffer *)
288 vzalloc(array_size(droq->max_count,
289 OCT_DROQ_RECVBUF_SIZE));
290 if (!droq->recv_buf_list) {
291 dev_err(&oct->pci_dev->dev, "Output queue recv buf list alloc failed\n");
292 goto init_droq_fail;
293 }
294
295 if (octeon_droq_setup_ring_buffers(oct, droq))
296 goto init_droq_fail;
297
298 droq->pkts_per_intr = c_pkts_per_intr;
299 droq->refill_threshold = c_refill_threshold;
300
301 dev_dbg(&oct->pci_dev->dev, "DROQ INIT: max_empty_descs: %d\n",
302 droq->max_empty_descs);
303
304 INIT_LIST_HEAD(&droq->dispatch_list);
305
306 /* For 56xx Pass1, this function won't be called, so no checks. */
307 oct->fn_list.setup_oq_regs(oct, q_no);
308
309 oct->io_qmask.oq |= BIT_ULL(q_no);
310
311 return 0;
312
313 init_droq_fail:
314 octeon_delete_droq(oct, q_no);
315 return 1;
316 }
317
318 /* octeon_create_recv_info
319 * Parameters:
320 * octeon_dev - pointer to the octeon device structure
321 * droq - droq in which the packet arrived.
322 * buf_cnt - no. of buffers used by the packet.
323 * idx - index in the descriptor for the first buffer in the packet.
324 * Description:
325 * Allocates a recv_info_t and copies the buffer addresses for packet data
326 * into the recv_pkt space which starts at an 8B offset from recv_info_t.
327 * Flags the descriptors for refill later. If available descriptors go
328 * below the threshold to receive a 64K pkt, new buffers are first allocated
329 * before the recv_pkt_t is created.
330 * This routine will be called in interrupt context.
331 * Returns:
332 * Success: Pointer to recv_info_t
333 * Failure: NULL.
334 */
octeon_create_recv_info(struct octeon_device * octeon_dev,struct octeon_droq * droq,u32 buf_cnt,u32 idx)335 static inline struct octeon_recv_info *octeon_create_recv_info(
336 struct octeon_device *octeon_dev,
337 struct octeon_droq *droq,
338 u32 buf_cnt,
339 u32 idx)
340 {
341 struct octeon_droq_info *info;
342 struct octeon_recv_pkt *recv_pkt;
343 struct octeon_recv_info *recv_info;
344 u32 i, bytes_left;
345 struct octeon_skb_page_info *pg_info;
346
347 info = (struct octeon_droq_info *)droq->recv_buf_list[idx].data;
348
349 recv_info = octeon_alloc_recv_info(sizeof(struct __dispatch));
350 if (!recv_info)
351 return NULL;
352
353 recv_pkt = recv_info->recv_pkt;
354 recv_pkt->rh = info->rh;
355 recv_pkt->length = (u32)info->length;
356 recv_pkt->buffer_count = (u16)buf_cnt;
357 recv_pkt->octeon_id = (u16)octeon_dev->octeon_id;
358
359 i = 0;
360 bytes_left = (u32)info->length;
361
362 while (buf_cnt) {
363 {
364 pg_info = &droq->recv_buf_list[idx].pg_info;
365
366 lio_unmap_ring(octeon_dev->pci_dev,
367 (u64)pg_info->dma);
368 pg_info->page = NULL;
369 pg_info->dma = 0;
370 }
371
372 recv_pkt->buffer_size[i] =
373 (bytes_left >=
374 droq->buffer_size) ? droq->buffer_size : bytes_left;
375
376 recv_pkt->buffer_ptr[i] = droq->recv_buf_list[idx].buffer;
377 droq->recv_buf_list[idx].buffer = NULL;
378
379 idx = incr_index(idx, 1, droq->max_count);
380 bytes_left -= droq->buffer_size;
381 i++;
382 buf_cnt--;
383 }
384
385 return recv_info;
386 }
387
388 /* If we were not able to refill all buffers, try to move around
389 * the buffers that were not dispatched.
390 */
391 static inline u32
octeon_droq_refill_pullup_descs(struct octeon_droq * droq,struct octeon_droq_desc * desc_ring)392 octeon_droq_refill_pullup_descs(struct octeon_droq *droq,
393 struct octeon_droq_desc *desc_ring)
394 {
395 u32 desc_refilled = 0;
396
397 u32 refill_index = droq->refill_idx;
398
399 while (refill_index != droq->read_idx) {
400 if (droq->recv_buf_list[refill_index].buffer) {
401 droq->recv_buf_list[droq->refill_idx].buffer =
402 droq->recv_buf_list[refill_index].buffer;
403 droq->recv_buf_list[droq->refill_idx].data =
404 droq->recv_buf_list[refill_index].data;
405 desc_ring[droq->refill_idx].buffer_ptr =
406 desc_ring[refill_index].buffer_ptr;
407 droq->recv_buf_list[refill_index].buffer = NULL;
408 desc_ring[refill_index].buffer_ptr = 0;
409 do {
410 droq->refill_idx = incr_index(droq->refill_idx,
411 1,
412 droq->max_count);
413 desc_refilled++;
414 droq->refill_count--;
415 } while (droq->recv_buf_list[droq->refill_idx].buffer);
416 }
417 refill_index = incr_index(refill_index, 1, droq->max_count);
418 } /* while */
419 return desc_refilled;
420 }
421
422 /* octeon_droq_refill
423 * Parameters:
424 * droq - droq in which descriptors require new buffers.
425 * Description:
426 * Called during normal DROQ processing in interrupt mode or by the poll
427 * thread to refill the descriptors from which buffers were dispatched
428 * to upper layers. Attempts to allocate new buffers. If that fails, moves
429 * up buffers (that were not dispatched) to form a contiguous ring.
430 * Returns:
431 * No of descriptors refilled.
432 */
433 static u32
octeon_droq_refill(struct octeon_device * octeon_dev,struct octeon_droq * droq)434 octeon_droq_refill(struct octeon_device *octeon_dev, struct octeon_droq *droq)
435 {
436 struct octeon_droq_desc *desc_ring;
437 void *buf = NULL;
438 u8 *data;
439 u32 desc_refilled = 0;
440 struct octeon_skb_page_info *pg_info;
441
442 desc_ring = droq->desc_ring;
443
444 while (droq->refill_count && (desc_refilled < droq->max_count)) {
445 /* If a valid buffer exists (happens if there is no dispatch),
446 * reuse the buffer, else allocate.
447 */
448 if (!droq->recv_buf_list[droq->refill_idx].buffer) {
449 pg_info =
450 &droq->recv_buf_list[droq->refill_idx].pg_info;
451 /* Either recycle the existing pages or go for
452 * new page alloc
453 */
454 if (pg_info->page)
455 buf = recv_buffer_reuse(octeon_dev, pg_info);
456 else
457 buf = recv_buffer_alloc(octeon_dev, pg_info);
458 /* If a buffer could not be allocated, no point in
459 * continuing
460 */
461 if (!buf) {
462 droq->stats.rx_alloc_failure++;
463 break;
464 }
465 droq->recv_buf_list[droq->refill_idx].buffer =
466 buf;
467 data = get_rbd(buf);
468 } else {
469 data = get_rbd(droq->recv_buf_list
470 [droq->refill_idx].buffer);
471 }
472
473 droq->recv_buf_list[droq->refill_idx].data = data;
474
475 desc_ring[droq->refill_idx].buffer_ptr =
476 lio_map_ring(droq->recv_buf_list[
477 droq->refill_idx].buffer);
478
479 droq->refill_idx = incr_index(droq->refill_idx, 1,
480 droq->max_count);
481 desc_refilled++;
482 droq->refill_count--;
483 }
484
485 if (droq->refill_count)
486 desc_refilled +=
487 octeon_droq_refill_pullup_descs(droq, desc_ring);
488
489 /* if droq->refill_count
490 * The refill count would not change in pass two. We only moved buffers
491 * to close the gap in the ring, but we would still have the same no. of
492 * buffers to refill.
493 */
494 return desc_refilled;
495 }
496
497 /** check if we can allocate packets to get out of oom.
498 * @param droq - Droq being checked.
499 * @return 1 if fails to refill minimum
500 */
octeon_retry_droq_refill(struct octeon_droq * droq)501 int octeon_retry_droq_refill(struct octeon_droq *droq)
502 {
503 struct octeon_device *oct = droq->oct_dev;
504 int desc_refilled, reschedule = 1;
505 u32 pkts_credit;
506
507 pkts_credit = readl(droq->pkts_credit_reg);
508 desc_refilled = octeon_droq_refill(oct, droq);
509 if (desc_refilled) {
510 /* Flush the droq descriptor data to memory to be sure
511 * that when we update the credits the data in memory
512 * is accurate.
513 */
514 wmb();
515 writel(desc_refilled, droq->pkts_credit_reg);
516
517 if (pkts_credit + desc_refilled >= CN23XX_SLI_DEF_BP)
518 reschedule = 0;
519 }
520
521 return reschedule;
522 }
523
524 static inline u32
octeon_droq_get_bufcount(u32 buf_size,u32 total_len)525 octeon_droq_get_bufcount(u32 buf_size, u32 total_len)
526 {
527 return DIV_ROUND_UP(total_len, buf_size);
528 }
529
530 static int
octeon_droq_dispatch_pkt(struct octeon_device * oct,struct octeon_droq * droq,union octeon_rh * rh,struct octeon_droq_info * info)531 octeon_droq_dispatch_pkt(struct octeon_device *oct,
532 struct octeon_droq *droq,
533 union octeon_rh *rh,
534 struct octeon_droq_info *info)
535 {
536 u32 cnt;
537 octeon_dispatch_fn_t disp_fn;
538 struct octeon_recv_info *rinfo;
539
540 cnt = octeon_droq_get_bufcount(droq->buffer_size, (u32)info->length);
541
542 disp_fn = octeon_get_dispatch(oct, (u16)rh->r.opcode,
543 (u16)rh->r.subcode);
544 if (disp_fn) {
545 rinfo = octeon_create_recv_info(oct, droq, cnt, droq->read_idx);
546 if (rinfo) {
547 struct __dispatch *rdisp = rinfo->rsvd;
548
549 rdisp->rinfo = rinfo;
550 rdisp->disp_fn = disp_fn;
551 rinfo->recv_pkt->rh = *rh;
552 list_add_tail(&rdisp->list,
553 &droq->dispatch_list);
554 } else {
555 droq->stats.dropped_nomem++;
556 }
557 } else {
558 dev_err(&oct->pci_dev->dev, "DROQ: No dispatch function (opcode %u/%u)\n",
559 (unsigned int)rh->r.opcode,
560 (unsigned int)rh->r.subcode);
561 droq->stats.dropped_nodispatch++;
562 }
563
564 return cnt;
565 }
566
octeon_droq_drop_packets(struct octeon_device * oct,struct octeon_droq * droq,u32 cnt)567 static inline void octeon_droq_drop_packets(struct octeon_device *oct,
568 struct octeon_droq *droq,
569 u32 cnt)
570 {
571 u32 i = 0, buf_cnt;
572 struct octeon_droq_info *info;
573
574 for (i = 0; i < cnt; i++) {
575 info = (struct octeon_droq_info *)
576 droq->recv_buf_list[droq->read_idx].data;
577 octeon_swap_8B_data((u64 *)info, 2);
578
579 if (info->length) {
580 info->length += OCTNET_FRM_LENGTH_SIZE;
581 droq->stats.bytes_received += info->length;
582 buf_cnt = octeon_droq_get_bufcount(droq->buffer_size,
583 (u32)info->length);
584 } else {
585 dev_err(&oct->pci_dev->dev, "DROQ: In drop: pkt with len 0\n");
586 buf_cnt = 1;
587 }
588
589 droq->read_idx = incr_index(droq->read_idx, buf_cnt,
590 droq->max_count);
591 droq->refill_count += buf_cnt;
592 }
593 }
594
595 static u32
octeon_droq_fast_process_packets(struct octeon_device * oct,struct octeon_droq * droq,u32 pkts_to_process)596 octeon_droq_fast_process_packets(struct octeon_device *oct,
597 struct octeon_droq *droq,
598 u32 pkts_to_process)
599 {
600 u32 pkt, total_len = 0, pkt_count, retval;
601 struct octeon_droq_info *info;
602 union octeon_rh *rh;
603
604 pkt_count = pkts_to_process;
605
606 for (pkt = 0; pkt < pkt_count; pkt++) {
607 u32 pkt_len = 0;
608 struct sk_buff *nicbuf = NULL;
609 struct octeon_skb_page_info *pg_info;
610 void *buf;
611
612 info = (struct octeon_droq_info *)
613 droq->recv_buf_list[droq->read_idx].data;
614 octeon_swap_8B_data((u64 *)info, 2);
615
616 if (!info->length) {
617 dev_err(&oct->pci_dev->dev,
618 "DROQ[%d] idx: %d len:0, pkt_cnt: %d\n",
619 droq->q_no, droq->read_idx, pkt_count);
620 print_hex_dump_bytes("", DUMP_PREFIX_ADDRESS,
621 (u8 *)info,
622 OCT_DROQ_INFO_SIZE);
623 break;
624 }
625
626 /* Len of resp hdr in included in the received data len. */
627 rh = &info->rh;
628
629 info->length += OCTNET_FRM_LENGTH_SIZE;
630 rh->r_dh.len += (ROUNDUP8(OCT_DROQ_INFO_SIZE) / sizeof(u64));
631 total_len += (u32)info->length;
632 if (opcode_slow_path(rh)) {
633 u32 buf_cnt;
634
635 buf_cnt = octeon_droq_dispatch_pkt(oct, droq, rh, info);
636 droq->read_idx = incr_index(droq->read_idx,
637 buf_cnt, droq->max_count);
638 droq->refill_count += buf_cnt;
639 } else {
640 if (info->length <= droq->buffer_size) {
641 pkt_len = (u32)info->length;
642 nicbuf = droq->recv_buf_list[
643 droq->read_idx].buffer;
644 pg_info = &droq->recv_buf_list[
645 droq->read_idx].pg_info;
646 if (recv_buffer_recycle(oct, pg_info))
647 pg_info->page = NULL;
648 droq->recv_buf_list[droq->read_idx].buffer =
649 NULL;
650
651 droq->read_idx = incr_index(droq->read_idx, 1,
652 droq->max_count);
653 droq->refill_count++;
654 } else {
655 nicbuf = octeon_fast_packet_alloc((u32)
656 info->length);
657 pkt_len = 0;
658 /* nicbuf allocation can fail. We'll handle it
659 * inside the loop.
660 */
661 while (pkt_len < info->length) {
662 int cpy_len, idx = droq->read_idx;
663
664 cpy_len = ((pkt_len + droq->buffer_size)
665 > info->length) ?
666 ((u32)info->length - pkt_len) :
667 droq->buffer_size;
668
669 if (nicbuf) {
670 octeon_fast_packet_next(droq,
671 nicbuf,
672 cpy_len,
673 idx);
674 buf = droq->recv_buf_list[
675 idx].buffer;
676 recv_buffer_fast_free(buf);
677 droq->recv_buf_list[idx].buffer
678 = NULL;
679 } else {
680 droq->stats.rx_alloc_failure++;
681 }
682
683 pkt_len += cpy_len;
684 droq->read_idx =
685 incr_index(droq->read_idx, 1,
686 droq->max_count);
687 droq->refill_count++;
688 }
689 }
690
691 if (nicbuf) {
692 if (droq->ops.fptr) {
693 droq->ops.fptr(oct->octeon_id,
694 nicbuf, pkt_len,
695 rh, &droq->napi,
696 droq->ops.farg);
697 } else {
698 recv_buffer_free(nicbuf);
699 }
700 }
701 }
702
703 if (droq->refill_count >= droq->refill_threshold) {
704 int desc_refilled = octeon_droq_refill(oct, droq);
705
706 if (desc_refilled) {
707 /* Flush the droq descriptor data to memory to
708 * be sure that when we update the credits the
709 * data in memory is accurate.
710 */
711 wmb();
712 writel(desc_refilled, droq->pkts_credit_reg);
713 }
714 }
715 } /* for (each packet)... */
716
717 /* Increment refill_count by the number of buffers processed. */
718 droq->stats.pkts_received += pkt;
719 droq->stats.bytes_received += total_len;
720
721 retval = pkt;
722 if ((droq->ops.drop_on_max) && (pkts_to_process - pkt)) {
723 octeon_droq_drop_packets(oct, droq, (pkts_to_process - pkt));
724
725 droq->stats.dropped_toomany += (pkts_to_process - pkt);
726 retval = pkts_to_process;
727 }
728
729 atomic_sub(retval, &droq->pkts_pending);
730
731 if (droq->refill_count >= droq->refill_threshold &&
732 readl(droq->pkts_credit_reg) < CN23XX_SLI_DEF_BP) {
733 octeon_droq_check_hw_for_pkts(droq);
734
735 /* Make sure there are no pkts_pending */
736 if (!atomic_read(&droq->pkts_pending))
737 octeon_schedule_rxq_oom_work(oct, droq);
738 }
739
740 return retval;
741 }
742
743 int
octeon_droq_process_packets(struct octeon_device * oct,struct octeon_droq * droq,u32 budget)744 octeon_droq_process_packets(struct octeon_device *oct,
745 struct octeon_droq *droq,
746 u32 budget)
747 {
748 u32 pkt_count = 0;
749 struct list_head *tmp, *tmp2;
750
751 octeon_droq_check_hw_for_pkts(droq);
752 pkt_count = atomic_read(&droq->pkts_pending);
753
754 if (!pkt_count)
755 return 0;
756
757 if (pkt_count > budget)
758 pkt_count = budget;
759
760 octeon_droq_fast_process_packets(oct, droq, pkt_count);
761
762 list_for_each_safe(tmp, tmp2, &droq->dispatch_list) {
763 struct __dispatch *rdisp = (struct __dispatch *)tmp;
764
765 list_del(tmp);
766 rdisp->disp_fn(rdisp->rinfo,
767 octeon_get_dispatch_arg
768 (oct,
769 (u16)rdisp->rinfo->recv_pkt->rh.r.opcode,
770 (u16)rdisp->rinfo->recv_pkt->rh.r.subcode));
771 }
772
773 /* If there are packets pending. schedule tasklet again */
774 if (atomic_read(&droq->pkts_pending))
775 return 1;
776
777 return 0;
778 }
779
780 /**
781 * Utility function to poll for packets. check_hw_for_packets must be
782 * called before calling this routine.
783 */
784
785 int
octeon_droq_process_poll_pkts(struct octeon_device * oct,struct octeon_droq * droq,u32 budget)786 octeon_droq_process_poll_pkts(struct octeon_device *oct,
787 struct octeon_droq *droq, u32 budget)
788 {
789 struct list_head *tmp, *tmp2;
790 u32 pkts_available = 0, pkts_processed = 0;
791 u32 total_pkts_processed = 0;
792
793 if (budget > droq->max_count)
794 budget = droq->max_count;
795
796 while (total_pkts_processed < budget) {
797 octeon_droq_check_hw_for_pkts(droq);
798
799 pkts_available = min((budget - total_pkts_processed),
800 (u32)(atomic_read(&droq->pkts_pending)));
801
802 if (pkts_available == 0)
803 break;
804
805 pkts_processed =
806 octeon_droq_fast_process_packets(oct, droq,
807 pkts_available);
808
809 total_pkts_processed += pkts_processed;
810 }
811
812 list_for_each_safe(tmp, tmp2, &droq->dispatch_list) {
813 struct __dispatch *rdisp = (struct __dispatch *)tmp;
814
815 list_del(tmp);
816 rdisp->disp_fn(rdisp->rinfo,
817 octeon_get_dispatch_arg
818 (oct,
819 (u16)rdisp->rinfo->recv_pkt->rh.r.opcode,
820 (u16)rdisp->rinfo->recv_pkt->rh.r.subcode));
821 }
822
823 return total_pkts_processed;
824 }
825
826 /* Enable Pkt Interrupt */
827 int
octeon_enable_irq(struct octeon_device * oct,u32 q_no)828 octeon_enable_irq(struct octeon_device *oct, u32 q_no)
829 {
830 switch (oct->chip_id) {
831 case OCTEON_CN66XX:
832 case OCTEON_CN68XX: {
833 struct octeon_cn6xxx *cn6xxx =
834 (struct octeon_cn6xxx *)oct->chip;
835 unsigned long flags;
836 u32 value;
837
838 spin_lock_irqsave
839 (&cn6xxx->lock_for_droq_int_enb_reg, flags);
840 value = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB);
841 value |= (1 << q_no);
842 octeon_write_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB, value);
843 value = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB);
844 value |= (1 << q_no);
845 octeon_write_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB, value);
846
847 /* don't bother flushing the enables */
848
849 spin_unlock_irqrestore
850 (&cn6xxx->lock_for_droq_int_enb_reg, flags);
851 }
852 break;
853 case OCTEON_CN23XX_PF_VID:
854 lio_enable_irq(oct->droq[q_no], oct->instr_queue[q_no]);
855 break;
856
857 case OCTEON_CN23XX_VF_VID:
858 lio_enable_irq(oct->droq[q_no], oct->instr_queue[q_no]);
859 break;
860 default:
861 dev_err(&oct->pci_dev->dev, "%s Unknown Chip\n", __func__);
862 return 1;
863 }
864
865 return 0;
866 }
867
octeon_register_droq_ops(struct octeon_device * oct,u32 q_no,struct octeon_droq_ops * ops)868 int octeon_register_droq_ops(struct octeon_device *oct, u32 q_no,
869 struct octeon_droq_ops *ops)
870 {
871 struct octeon_config *oct_cfg = NULL;
872 struct octeon_droq *droq;
873
874 oct_cfg = octeon_get_conf(oct);
875
876 if (!oct_cfg)
877 return -EINVAL;
878
879 if (!(ops)) {
880 dev_err(&oct->pci_dev->dev, "%s: droq_ops pointer is NULL\n",
881 __func__);
882 return -EINVAL;
883 }
884
885 if (q_no >= CFG_GET_OQ_MAX_Q(oct_cfg)) {
886 dev_err(&oct->pci_dev->dev, "%s: droq id (%d) exceeds MAX (%d)\n",
887 __func__, q_no, (oct->num_oqs - 1));
888 return -EINVAL;
889 }
890
891 droq = oct->droq[q_no];
892 memcpy(&droq->ops, ops, sizeof(struct octeon_droq_ops));
893
894 return 0;
895 }
896
octeon_unregister_droq_ops(struct octeon_device * oct,u32 q_no)897 int octeon_unregister_droq_ops(struct octeon_device *oct, u32 q_no)
898 {
899 struct octeon_config *oct_cfg = NULL;
900 struct octeon_droq *droq;
901
902 oct_cfg = octeon_get_conf(oct);
903
904 if (!oct_cfg)
905 return -EINVAL;
906
907 if (q_no >= CFG_GET_OQ_MAX_Q(oct_cfg)) {
908 dev_err(&oct->pci_dev->dev, "%s: droq id (%d) exceeds MAX (%d)\n",
909 __func__, q_no, oct->num_oqs - 1);
910 return -EINVAL;
911 }
912
913 droq = oct->droq[q_no];
914
915 if (!droq) {
916 dev_info(&oct->pci_dev->dev,
917 "Droq id (%d) not available.\n", q_no);
918 return 0;
919 }
920
921 droq->ops.fptr = NULL;
922 droq->ops.farg = NULL;
923 droq->ops.drop_on_max = 0;
924
925 return 0;
926 }
927
octeon_create_droq(struct octeon_device * oct,u32 q_no,u32 num_descs,u32 desc_size,void * app_ctx)928 int octeon_create_droq(struct octeon_device *oct,
929 u32 q_no, u32 num_descs,
930 u32 desc_size, void *app_ctx)
931 {
932 struct octeon_droq *droq;
933 int numa_node = dev_to_node(&oct->pci_dev->dev);
934
935 if (oct->droq[q_no]) {
936 dev_dbg(&oct->pci_dev->dev, "Droq already in use. Cannot create droq %d again\n",
937 q_no);
938 return 1;
939 }
940
941 /* Allocate the DS for the new droq. */
942 droq = vmalloc_node(sizeof(*droq), numa_node);
943 if (!droq)
944 droq = vmalloc(sizeof(*droq));
945 if (!droq)
946 return -1;
947
948 memset(droq, 0, sizeof(struct octeon_droq));
949
950 /*Disable the pkt o/p for this Q */
951 octeon_set_droq_pkt_op(oct, q_no, 0);
952 oct->droq[q_no] = droq;
953
954 /* Initialize the Droq */
955 if (octeon_init_droq(oct, q_no, num_descs, desc_size, app_ctx)) {
956 vfree(oct->droq[q_no]);
957 oct->droq[q_no] = NULL;
958 return -1;
959 }
960
961 oct->num_oqs++;
962
963 dev_dbg(&oct->pci_dev->dev, "%s: Total number of OQ: %d\n", __func__,
964 oct->num_oqs);
965
966 /* Global Droq register settings */
967
968 /* As of now not required, as setting are done for all 32 Droqs at
969 * the same time.
970 */
971 return 0;
972 }
973
