Searched refs:mul_u32_u32 (Results 1 – 13 of 13) sorted by relevance
| /Linux-v5.4/include/linux/ |
| D | math64.h | 164 #ifndef mul_u32_u32
168 static inline u64 mul_u32_u32(u32 a, u32 b) in mul_u32_u32() function
201 ret = mul_u32_u32(al, mul) >> shift; in mul_u64_u32_shr()
203 ret += mul_u32_u32(ah, mul) << (32 - shift); in mul_u64_u32_shr()
227 rl.ll = mul_u32_u32(a0.l.low, b0.l.low); in mul_u64_u64_shr()
228 rm.ll = mul_u32_u32(a0.l.low, b0.l.high); in mul_u64_u64_shr()
229 rn.ll = mul_u32_u32(a0.l.high, b0.l.low); in mul_u64_u64_shr()
230 rh.ll = mul_u32_u32(a0.l.high, b0.l.high); in mul_u64_u64_shr()
270 rl.ll = mul_u32_u32(u.l.low, mul); in mul_u64_u32_div()
271 rh.ll = mul_u32_u32(u.l.high, mul) + rl.l.high; in mul_u64_u32_div()
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| /Linux-v5.4/arch/x86/include/asm/ |
| D | div64.h | 63 static inline u64 mul_u32_u32(u32 a, u32 b) in mul_u32_u32() function
72 #define mul_u32_u32 mul_u32_u32 macro
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| /Linux-v5.4/drivers/gpu/drm/i915/ |
| D | i915_fixed.h | 79 tmp = mul_u32_u32(val, mul.val); in mul_round_up_u32_fixed16()
91 tmp = mul_u32_u32(val.val, mul.val); in mul_fixed16()
122 tmp = mul_u32_u32(val, mul.val); in mul_u32_fixed16()
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| D | i915_pmu.c | 221 sample->cur += mul_u32_u32(val, mul); in add_sample_mult()
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| D | i915_irq.c | 877 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, in __intel_get_crtc_scanline_from_timestamp()
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| D | intel_pm.c | 691 ret = mul_u32_u32(pixel_rate, cpp * latency); in intel_wm_method1()
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| /Linux-v5.4/drivers/gpu/drm/i915/selftests/ |
| D | i915_random.h | 48 return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro)); in i915_prandom_u32_max_state()
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| /Linux-v5.4/drivers/gpu/drm/ |
| D | drm_rect.c | 57 u64 tmp = mul_u32_u32(src, dst - clip); in clip_scaled()
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| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_color.c | 129 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30; in ctm_mult_by_limited()
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| D | intel_dpll_mgr.c | 2792 tmp = mul_u32_u32(dco_khz, 47 * 32); in icl_calc_mg_pll_state()
2796 tmp = mul_u32_u32(dco_khz, 1000); in icl_calc_mg_pll_state()
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| D | intel_display.c | 580 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), in chv_calc_dpll_params()
965 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, in chv_find_best_dpll()
2405 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]), in intel_fb_offset_to_xy()
2783 if (mul_u32_u32(max_size, tile_size) > obj->base.size) { in intel_fill_fb_info()
2785 mul_u32_u32(max_size, tile_size), obj->base.size); in intel_fill_fb_info()
7399 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h), in ilk_pipe_pixel_rate()
7519 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); in compute_m_n()
11389 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); in intel_dotclock_calculate()
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| D | intel_panel.c | 475 target_val = mul_u32_u32(source_val - source_min, in scale()
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| D | intel_dp.c | 499 return div_u64(mul_u32_u32(mode_clock, 1000000U), in intel_dp_mode_to_fec_clock()
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