Searched refs:mtk_hdmi_phy_mask (Results 1 – 4 of 4) sorted by relevance
/Linux-v5.4/drivers/gpu/drm/mediatek/ |
D | mtk_mt2701_hdmi_phy.c | 131 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC), in mtk_hdmi_pll_set_rate() 133 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR), in mtk_hdmi_pll_set_rate() 135 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV), in mtk_hdmi_pll_set_rate() 137 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL), in mtk_hdmi_pll_set_rate() 139 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV), in mtk_hdmi_pll_set_rate() 141 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN), in mtk_hdmi_pll_set_rate() 143 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP), in mtk_hdmi_pll_set_rate() 145 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC), in mtk_hdmi_pll_set_rate() 147 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR), in mtk_hdmi_pll_set_rate() 151 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS), in mtk_hdmi_pll_set_rate() [all …]
|
D | mtk_mt8173_hdmi_phy.c | 232 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate() 235 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate() 238 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, in mtk_hdmi_pll_set_rate() 240 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate() 243 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, in mtk_hdmi_pll_set_rate() 245 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, in mtk_hdmi_pll_set_rate() 263 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, in mtk_hdmi_pll_set_rate() 272 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, in mtk_hdmi_pll_set_rate() 275 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, in mtk_hdmi_pll_set_rate() 282 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, in mtk_hdmi_pll_set_rate()
|
D | mtk_hdmi_phy.h | 49 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
D | mtk_hdmi_phy.c | 40 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, in mtk_hdmi_phy_mask() function
|