Searched refs:msm_readl (Results 1 – 15 of 15) sorted by relevance
84 return msm_readl(gmu->mmio + (offset << 2)); in gmu_read()105 val = (u64) msm_readl(gmu->mmio + (lo << 2)); in gmu_read64()106 val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32); in gmu_read64()
180 msm_readl((ptr) + ((offset) << 2))
124 return msm_readl(hdmi->mmio + reg); in hdmi_read()129 return msm_readl(hdmi->qfprom_mmio + reg); in hdmi_qfprom_read()175 return msm_readl(phy->mmio + reg); in hdmi_phy_read()
244 return msm_readl(pll->mmio + reg); in pll_read()
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
221 return msm_readl(gpu->mmio + (reg << 2)); in gpu_read()250 val = (u64) msm_readl(gpu->mmio + (lo << 2)); in gpu_read64()251 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); in gpu_read64()
411 u32 msm_readl(const void __iomem *addr);
160 u32 msm_readl(const void __iomem *addr) in msm_readl() function
18 #define edp_read(offset) msm_readl((offset))
13 #define dsi_phy_read(offset) msm_readl((offset))
49 return msm_readl(reg); in pll_read()
58 return msm_readl(mdp4_kms->mmio + reg); in mdp4_read()
38 return msm_readl(mdp5_mdss->mmio + reg); in mdss_read()
179 return msm_readl(mdp5_kms->mmio + reg); in mdp5_read()
49 ver = msm_readl(base + REG_DSI_VERSION); in dsi_get_version()67 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); in dsi_get_version()72 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); in dsi_get_version()188 return msm_readl(msm_host->ctrl_base + reg); in dsi_read()
