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Searched refs:mmVM_CONTEXT1_CNTL (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgmc_v6_0.c415 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_set_fault_enable_default()
428 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_set_fault_enable_default()
564 WREG32(mmVM_CONTEXT1_CNTL, in gmc_v6_0_gart_enable()
613 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v6_0_gart_disable()
1074 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1076 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
1082 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1084 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
Dgmc_v7_0.c498 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_set_fault_enable_default()
511 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_set_fault_enable_default()
663 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_gart_enable()
668 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_gart_enable()
718 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v7_0_gart_disable()
1222 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1224 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1232 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1234 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
Dgmc_v8_0.c723 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_set_fault_enable_default()
738 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_set_fault_enable_default()
906 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_gart_enable()
918 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_gart_enable()
962 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v8_0_gart_disable()
1394 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1396 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1404 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1406 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
Dgfxhub_v1_0.c215 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); in gfxhub_v1_0_setup_vmid_config()
241 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); in gfxhub_v1_0_setup_vmid_config()
Dmmhub_v1_0.c247 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); in mmhub_v1_0_setup_vmid_config()
273 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); in mmhub_v1_0_setup_vmid_config()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_d.h546 #define mmVM_CONTEXT1_CNTL 0x505 macro
Dgmc_8_2_d.h604 #define mmVM_CONTEXT1_CNTL 0x505 macro
Dgmc_6_0_d.h1231 #define mmVM_CONTEXT1_CNTL 0x0505 macro
Dgmc_7_1_d.h579 #define mmVM_CONTEXT1_CNTL 0x505 macro
Dgmc_8_1_d.h602 #define mmVM_CONTEXT1_CNTL 0x505 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_9_1_offset.h1358 #define mmVM_CONTEXT1_CNTL … macro
Dmmhub_9_3_0_offset.h1342 #define mmVM_CONTEXT1_CNTL … macro
Dmmhub_1_0_offset.h1326 #define mmVM_CONTEXT1_CNTL … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1215 #define mmVM_CONTEXT1_CNTL … macro
Dgc_9_1_offset.h1248 #define mmVM_CONTEXT1_CNTL … macro
Dgc_9_2_1_offset.h1186 #define mmVM_CONTEXT1_CNTL … macro