Searched refs:mmUVD_VCPU_CACHE_SIZE2 (Results 1 – 15 of 15) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 93 #define mmUVD_VCPU_CACHE_SIZE2 0x3D3B macro
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| D | uvd_4_2_d.h | 65 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 macro
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| D | uvd_5_0_d.h | 71 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 macro
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| D | uvd_6_0_d.h | 87 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 macro
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| D | uvd_7_0_offset.h | 186 #define mmUVD_VCPU_CACHE_SIZE2 … macro
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 374 #define mmUVD_VCPU_CACHE_SIZE2 … macro
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| D | vcn_2_5_offset.h | 683 #define mmUVD_VCPU_CACHE_SIZE2 … macro
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| D | vcn_2_0_0_offset.h | 624 #define mmUVD_VCPU_CACHE_SIZE2 … macro
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| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v4_2.c | 561 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v4_2_mc_resume()
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| D | uvd_v5_0.c | 278 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v5_0_mc_resume()
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| D | uvd_v7_0.c | 694 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, in uvd_v7_0_mc_resume()
837 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), in uvd_v7_0_sriov_start()
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| D | vcn_v2_0.c | 402 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_0_mc_resume()
484 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
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| D | vcn_v1_0.c | 333 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v1_0_mc_resume_spg_mode()
407 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, in vcn_v1_0_mc_resume_dpg_mode()
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| D | uvd_v6_0.c | 604 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v6_0_mc_resume()
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| D | vcn_v2_5.c | 418 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_mc_resume()
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