Searched refs:mmUVD_VCPU_CACHE_SIZE0 (Results 1 – 15 of 15) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 91 #define mmUVD_VCPU_CACHE_SIZE0 0x3D37 macro
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| D | uvd_4_2_d.h | 61 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
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| D | uvd_5_0_d.h | 67 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
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| D | uvd_6_0_d.h | 83 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
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| D | uvd_7_0_offset.h | 178 #define mmUVD_VCPU_CACHE_SIZE0 … macro
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| /Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 366 #define mmUVD_VCPU_CACHE_SIZE0 … macro
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| D | vcn_2_5_offset.h | 675 #define mmUVD_VCPU_CACHE_SIZE0 … macro
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| D | vcn_2_0_0_offset.h | 616 #define mmUVD_VCPU_CACHE_SIZE0 … macro
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| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v4_2.c | 550 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v4_2_mc_resume()
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| D | uvd_v5_0.c | 267 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v5_0_mc_resume()
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| D | vcn_v2_0.c | 386 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_0_mc_resume()
448 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
451 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
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| D | uvd_v7_0.c | 680 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v7_0_mc_resume()
823 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); in uvd_v7_0_sriov_start()
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| D | vcn_v1_0.c | 317 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v1_0_mc_resume_spg_mode()
387 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
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| D | uvd_v6_0.c | 593 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v6_0_mc_resume()
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| D | vcn_v2_5.c | 402 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_5_mc_resume()
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